AK4497 Datasheet, PDF (24/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
(Ta=-40~85C; VDDL/R=4.755.25V, TVDD=AVDD=1.73.6V, DVDD=1.7~1.98V, C_L=20pF, PSNpin=L,
AFSDbit= "1")
Parameter
Symbol Min.
Typ.
Max.
Unit
Master Clock Timing (FS Auto Detect Mode)
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
7.68
40
9.155
9.155
49.152
60
MHz
%
nsec
nsec
LRCK Clock Timing (FS Auto Detect Mode) (Note 30)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
fsn
30
54
kHz
Double Speed Mode
fsd
88.2
108
kHz
Quad Speed Mode
Oct speed mode
fsq
176.4
216
kHz
fso
384
kHz
Hex speed mode
fsh
768
kHz
Duty Cycle
Duty
45
55
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
fsn
30
54
kHz
Double Speed Mode
Quad Speed Mode
fsd
88.2
fsq
176.4
108
kHz
216
kHz
High time
tLRH 1/128fs
nsec
Low time
tLRL 1/128fs
ns
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
fsn
30
54
kHz
Double Speed Mode
fsd
108
kHz
High time
Low time
tLRH
tLRL
1/256fs
1/256fs
nsec
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
fsn
30
54
kHz
High time
tLRH 1/512fs
nsec
Low time
tLRL 1/512fs
nsec
Note 30. Normal operation is not guaranteed if a frequency not shown above is input to the LRCK when
the AK4497 is in Sampling Frequency Auto Detect Mode.
Rev. 0.1
- 24 -
2015/11