AK4497 Datasheet, PDF (44/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
[2] External Digital Filter Mode (EXDF mode)
The external clocks that are required in EXDF mode are MCLK, BCK and WCK. The BCK and MCLK
clocks must be the same frequency and must not burst. BCK and MCLK frequencies for each sampling
speed are shown in Table 22. ECS bit selects WCK frequency from 384kHz and 768kHz. DW indicates
the number of BCK in one WCK cycle.
All circuits except the internal LDO are automatically placed in power-down state when MCLK edge is not
detected for more than 1us during a normal operation (PDN pin =“H”), and the analog output becomes
Hi-Z state. The power-down state is released and the AK4497 starts operation by inputting MCLK again.
In this case, register settings are not initialized.
When the reset is released (PDN pin = “L” → “H”), the AK4497 is in power-down state until MCLK, BCK
and WCK are input.
Sampling
Speed[kHz]
44.1(30~48)
44.1(30~48)
128fs
N/A
N/A
N/A
96(54~96)
96(54~96)
192(108~192)
192(108~192)
12.28
8
32
24.576
32
N/A
Table 22. System Clock Example (EXDF mode)
192fs
N/A
N/A
N/A
MCLK&BCK [MHz]
256fs
N/A
384fs
N/A
11.2896
32
24.576
32
16.9344
48
36.864
48
512fs
22.5792
32
N/A
N/A
768fs
33.8688
48
33.8688
96
N/A
18.432
N/A
36.864
N/A
N/A
48
96
36.864
N/A
N/A
48
36.864
N/A
N/A
96
N/A
N/A
N/A
N/A
WCK
16fs
DW
8fs
DW
8fs
DW
4fs
DW
4fs
DW
2fs
DW
ECS
0 (default)
1
0
1
0
1
Rev. 0.1
- 44 -
2015/11