AK4497 Datasheet, PDF (73/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
■ Synchronize Function (PCM, EXDF)
The AK4497 has a function that resets the internal counter to keep the timing of falling edge of the internal
clock CLK1 and the external clock edge in a certain range. With this synchronize function, group delays
between each device can be kept within 4/256fs when using multiple AK4497’s.
Clock synchronize function becomes valid when input data of both L and R channels are “0” for 8192
times continuously in PCM mode or EXDF mode, when both L and R channels become “0” and kept for
8192 times continuously by attenuation or when RSTN bit = “0”. In PCM mode, the internal counter is
synchronized with a rising edged of LRCK (falling edge of LRCK in I2C mode), and it is synchronized with
a rising edge of WCK in EXDF mode. In this case, the analog output has the same voltage as VCML/R.
This function is disabled by setting SYNCE bit = “0” in register control mode. Figure 57 shows a
synchronizing sequence when the input data is “0” for 8192 times continuously. Figure 58 shows a
synchronizing sequence by RSTN bit.
D/A In
(Digital)
SMUTE
ATT_Level
Attenuation
GD
AOUT
(1)
(1)
-
GD
GD
(4)
Both DZFL/R pin
Internal Counter
Reset
Internal
Data
(2)
8192/fs
SYNC
Operation (2)
2~3/fs (3)
(2)
8192/fs
SYNC
Operation (2)
(5)
Notes:
(1) Regarding ATT Transition time, refer to “■ Output Volume (PCM, DSD, EXDF)”.
(2) When both L and R channels data are “0” for 8192 times continuously, the DZFL and DZFR pins
become “H” and the synchronize function is valid.
(3) Internal data is fixed to “0” forcibly for 2 to 3/fs when internal counter is reset.
(4) A click noise may occur when the internal counter is reset. This noise is output even if a “0” data is
input. Mute the analog output externally if this click noise affects the system performance.
(5) When the internal clock and external clock are in synchronization, the internal counter is not reset
even if the synchronize function is valid.
Figure 57. Synchronizing Sequenc by Continuous “0” Data Input for 8192 Times
Rev. 0.1
- 73 -
2015/11