AK4497 Datasheet, PDF (69/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
(9) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes
2~3/fs when changing RSTN bit to “1”. The system timing example of power up/down when not
using LDO (LODE pin = “L”) is shown in Figure 53. When the LDOE pin= “L”, 1.8V (DVDD), 3.3V
(AVDD, TVDD) and 5V (VDDL, VDDR, VREFHL, VREFHR) power supplies should be powered up
at the same time, otherwise power up the 3.3V power supplies (AVDD, TVDD) first, 1.8V power
supply (DVDD) next and 5V power supplies (VDDL/R, VREFHL/R) last.
Power
(TVDD,AVDD)
Power
（DVDD）
Power
(VDDL/R,VREFHL/R)
PDN pin
(1)
Internal PDN
RSTN bit
Internal State
(Resister
(Clock devider)
(8)
Power Off
(9)
Internal State
(Digital Core)
Power Off
DAC In
(Digital)
DAC Out
(Analog)
(4)
(5)
Clock In
Don’t care
MCLK,LRCK,BICK
Normal Operation
Normal Operation
“0”data
GD
Power Off
(9)
Power Off
“0”data
GD
(5)
(4)
Don’t care
DZFL/R
(7)
Figure 53. Power-down/up Sequence Example (Resister Control Mode, LDOE pin= “H”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal shutdown switch is powered up after the PDN pin = “H” when the LDOE pin= “L”. The
internal circuit will start operation after the shutdown switch is ON (max. 1us).
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
(7) The DZFL/R pins are “L” in power-down mode (PDN pin = “L”).
(8) The clock divider is powered up in about 4/fs after the internal PDN is released.
(9) It takes 3~4/fs until the internal RSTN is changed when changing RSTN bit to “0” and it takes
2~3/fs when changing RSTN bit to “1”.
Rev. 0.1
- 69 -
2015/11