AK4497 Datasheet, PDF (75/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
■ Register Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Pins (pin control mode) or registers (register control mode) can control the functions of the AK4497. In pin
control mode, the register setting is ignored, and in register control mode the pin settings are ignored.
When the state of the PSN pin is changed, the AK4497 should be powered down by the PDN pin.
Otherwise, malfunctions may occur since previous settings are not initialized. The register control
interface is enabled by the PSN pin = “L”. Internal registers may be written to through 3-wire µP interface
pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2-bits, C1/0),
Read/Write (1-bit; fixed to “1”, write only), Register address (MSB first, 5-bits) and Control data (MSB first,
8-bits). The data is output on a falling edge of CCLK and the data is received on a rising edge of CCLK.
The writing of data is valid when CSN “”. The clock speed of CCLK is 5MHz (max).
Setting the PDN pin to “L” resets the registers to their default values. In register control mode, the digital
block except control registers and clock divider is reset by setting RSTN bit to “0”. In this case, the register
values are not initialized.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1 bit =CAD1 pin, C0 bit =CAD0 pin)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 59. Control I/F Timing
* The AK4497 does not support read commands in 3-wire serial control mode.
* When the AK4497 is in power down mode (PDN pin = “L”), writing into control registers is prohibited.
* The control data cannot be written when the CCLK rising edge is 15 times or less, or 17 times or more
during CSN is “L”.
Rev. 0.1
- 75 -
2015/11