AK8857VQ Datasheet, PDF (90/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Output Pin Control 1 A Register (R/W) [Sub Address 0x11] (A block register)
Output Pin Control 1 B Register (R/W) [Sub Address 0x29] (B block register)
A block output pin status setting register.
Sub Address 0x11, 0x29
bit 7
bit 6
bit 5
HDACTSELA
Reserved Reserved
HDACTSELB
Default Value
0
0
0
bit 4
VDACTSELA
VDACTSELB
0
bit 3
FIELDA
FIELDB
0
bit 2
DVALIDA
DVALIDB
0
Default Value : 0x00
bit 1
bit 0
VDACTA _HDACTA
VDACTB ^HDACTB
0
0
Output Control 1 A/B Register Definition
Bit Register Name
bit 0 HDACTA/B
HD_ACT_A/B Pin
Polarity
bit 1 VDACTA/B
VD_ACT_A/B Pin
Polarity
bit 2 DVALIDA/B
DVALID_A/B Pin
Polarity
bit 3 FIELDA/B
FIELD_A/B Pin Polarity
bit 4 VDACTSELA/B VD/ VACT Select_A/B
bit 5 HDACTSELA/B HD/ HACT Select_A/B
bit 6
~ Reserved
bit 7
Reserved
R/W Definition
HD_ACT_A/B pin output polarity setting.
R/W [0] : Active Low
[1] : Active High
VD_ACT_A/B pin output polarity setting.
R/W [0]: Active Low
[1]: Active High
DVALID_A/B pin output polarity setting.
R/W [0]: Active Low
[1]: Active High
FIELD_A/B pin output polarity setting.
R/W [0]: Active Low
[1]: Active High
VD_ACT_A/B pin output signal selection :
R/W [0] : VD signal is output.
[1] : VACT signal is output.
HD_ACT_A/B pin output signal selection :
R/W [0] : HD signal is output.
[1] : HACT signal is output.
R/W Reserved
Note: Output control via pins OE_A, OE_B, PDN and RSTN takes priority, regardless of the above
settings.
MS1189-E-01
-90-
2010/12