AK8857VQ Datasheet, PDF (61/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Automatic setup processing
In auto detection mode, the AK8857 can perform automatic setup processing in accordance with the
detected signal.
Setup processing of the signal to be decoded consists of the following.
Luminance signal:
Y=(Y-7.5)/0.925
Color signal: U=U/0.925, V=V/0.925
Automatic setup processing (AK8857 in auto detection mode)
Register setting
Detected signal
Setup-bit
STUPATOFF-bit
(Automatic setup
processing)
[0]
NTSC-M,J
[0]
PAL-B,D,G,H,I,N
[1]
PAL-Nc , 60
SECAM
[0]
[1]
[1]
Detected signal setup processing
status
Disable
Disable
Enable
Enable
PAL-M
NTSC-4.43
[0]
[0]
[1]
[0]
[1]
[1]
Enable
Disable
Enable
Enable
In the auto detection mode, the setup processing status will be determined by the register setting on
the basis of the detected signal category, with no detection as to the presence or absence of input
signal setup.
PGA (programmable gain amp)
The AK8857 digital PGA is buit internally.
The setting value can be set in range of −3dB to 10dB using ADC output data.
The register default setting is 0x1F (=0dB).
When analog video signal (0.5Vpp) is input to AIN ch, the setting value becomes the default value.
G
=
20
log _{⎢⎣⎡} ^0.625
−
{0.006× (31
0.625
−
PGA)}⎤
⎥⎦
GÉ¿PGA gain(dB)
PGAÉ¿PGA register setting(Dec.)
○PGA1[7:0]-bit : Sets the PGA value.
○PGA2[7:0]-bit : Sets the PGA value.
CVBS input : PGA1 is enable for A Block data output and PGA2 is enable for B Block data output.
S-video input : PGA1 is enable for luminance signal and PGA2 is enable for color signal.
Notes : If the output of A block and B block are selected from the same AIN ch, only PGA1 setting
is valid and PGA2 is not valid.
This register can read the AGC setting value.
If AGC is enabled, the PGA[7:0]-bits setting value has no effect, and the PGA setting can be
manually entered in the register only if AGC is disabled.
Signal input to the AK8857 should be made with the input level attenuated approximately 39% (-8.19
dB) by resistance splitting.
MS1189-E-01
-61-
2010/12