AK8857VQ Datasheet, PDF (75/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Register
bit 5 REGSEL
Select
bit 6 P1DRV0
~~
bit 7 P1DRV1
PVDD1
Drive
Common register setting method selection (*2)
R / W [0]: A block : Write/ Read enable
[1]: B block : Write/ Read enable
The digital P1 output pin buffer drive setting is set according
to PVDD1 input voltage setting.(*3)
[P1DRV1: P1DRV0]
R / W [00]: PVDD1 = 3.0 ~ 3.6V
[01]: PVDD1 = 2.3 ~ 2.7V
[10]: Reserved
[11]: PVDD1 = 1.7 ~ 2.0V
(*1) If [Non-decode] is select at the output block, the output pins will be in powersave mode and the
internal digital circuit operational is stop. This will save the power consumption.
(*2) If the output of A block and B block is selected from the same channel of input video signal, the
setting of Sub-address0x01 [AFE Control Register] register only enable if REGSEL=[0] and
disable if REGSEL=[1].
During S-video signal decode, the output block register setting is enable if REGSEL=[0] and
disable if REGSEL=[1].
(*3) Digital P1 pin: DATA_A[7:0], HD_ACT_A, VD_ACT_A, DVALID_A, FIELD_A,
DATA_B[7:0], HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B, DTCLK pin.
MS1189-E-01
-75-
2010/12