AK8857VQ Datasheet, PDF (89/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Output Pin Control 0 A Register (R/W) [Sub Address 0x10] (A block register)
Output Pin Control 0 B Register (R/W) [Sub Address 0x28] (B block register)
A block output pin output status setting
Sub Address 0x10, 0x28
bit 7
bit 6 bit 5
Reserved
FLA _HDACTLA
FLB ^HDACTLB
Default Value
0
0
0
bit 4 bit 3
NLA DVALIDLA
NLB DVALIDLB
0
0
bit 2
VDACTLA
VDACTLB
Default Value: 0x00
bit 1
bit 0
DOA1
DOB1
DOA0
DOB0
0
0
0
Output Control 0 A/B Register Definition
Bit Register Name
bit 0 DOA/B 0
~
~
bit 1 DOA/B 1
Data Output _A/B
bit 2 VDACTLA/B
VD/ VACT Low_A/B
bit 3 DVALIDLA/B
DVALID Low_A/B
bit 4 NLA/B
NSIG Low_A/B
bit 5 HDACTLA/B
HD/HACT Low_A/B
bit 6 FLA/B
bit 7 Reserved
FIELD_A/B
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Definition
[00]: Normal output
[01]: DATA_A/B [7: 0] pin output fixed at Low
[10]: Black level output
[11]: Blue level output
[0] : Normal output
[1]: VD_ACT_A/B pin output fixed at low.
[0] : Normal output
[1]: DVALID_A/B pin output fixed at low.
[0] : Normal output
[1] : NSIG_A/B pin output fixed at low
[0] : Normal output
[1]: HD_ACT_A/B pin output fixed at low.
[0] : Normal output
[1] : FIELD_A/B pin output fixed at low
Reserved
Note: Output control via pins OE_A, OE_B, PDN, RSTN and AINSEL[4:0] (Non-decode) takes priority,
regardless of the above settings.
MS1189-E-01
-89-
2010/12