AK8857VQ Datasheet, PDF (77/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Output Control Register (R/W) [Sub Address 0x02] (Common register)
Output data setting register.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x02
bit 7
bit 6
VBIDEC1 VBIDEC0
Default Value
0
0
bit 5
SLLVL
bit 4
TRSVSEL
0
0
bit 3
601LIMIT
0
Default Value: 0x00
bit 2
bit 1
bit 0
VBIL2 VBIL1 VBIL0
0
0
0
Output Format Register Definition
Bit Register Name
bit 0 VBIL0
~
~
bit 2 VBIL2
Vertical Blanking
Length
bit 3 601LIMIT
601 Output Limit
R/W Definition
VACT signal active starting position adjustment.
[ VBIL2 : VBIL0 ]
[000]: Default
[001]: 1Line (2Line*) advance
R/W
[010]: 2Line (4Line*) advance
[011]: 3Line (6Line*) advance
[100]: 4Line (8Line*) advance
[101]: 5Line (10Line*) advance
[110]: 6Line (12Line*) advance
[111]: 7Line (14Line*) advance
Output data code limit (Min-Max) setting
R/W [0] : 1-254 (Y/Cb/Cr)
[1] : 16-235 (Y) /16-240 (Cb/Cr)
Setting of lines for “Time reference signal” V-bit
value change in ITU-R BT.656 format
bit 4 TRSVSEL
Time Reference
Signal V Select
With 525-line input
Setting [0]: V=1 (lines 1~9 and 264~272)
V=0 (lines 10~263 and 273~525)
R/W Setting [1]: V=1 (lines 1~19 and 264~282)
V=0 (lines 20~263 and 283~525)
bit 5 SLLVL
bit 6 VBIDEC0
~
~
bit 7 VBIDEC1
Slice Level
VBI Decode
With 625-line input
Always (regardless of setting in this register):
V=1 (lines 1~22 and 311~335)
V=0 (lines 23~310 and 336~623)
Slice level setting
R/W [0] : Slice level approx. 25 IRE
[1] : Slice level approx. 50 IRE
Setting for type of data output during interval set in
Vertical Blanking Interval register *
[ VBIDEC1 : VBIDEC0 ]
R/W [00] : Black level data output
[01] : Monochrome data output
[10] : Slice result data output
[11] : Reserved
*Only support progressive output size of ITU-R BT.601, VGA, WVGA format.
MS1189-E-01
-77-
2010/12