AK8857VQ Datasheet, PDF (2/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

1.Functional Block Diagram
[AK8857VQ]
TEST0 TEST1
XTI XTO
SELA SDA SCL PDN RSTN
OE_A OE_B
AIN1
AIN2
AIN3
AIN4
MUX
TEST
LOGIC
Clock Module
PLL
Microprocessor
Interface
CLAMP AAF
CLAMP AAF
MUX
11-bit
ADC ^MUX
Digital Decimation
PGA1
Filter
Digital Decimation
PGA2
Filter
Sync
Separation
Sync
Separation
Composite Decode x 2
or
Y/C Docode x 1
Scaling
&
I/P
Buffer
VREF
VRP VCOM VRN IREF
AVDD
AVSS
DVDD
DVSS
PVDD1
PVDD2
DATA_A[7:0]
HD_ACT_A
VD_ACT_A
DVALID_A
FIELD_A
DTCLK
DATA_B[7:0]
HD_ACT_B
VD_ACT_B
DVALID_B
FIELD_B
NSIG_A
NSIG_B
In this specification, the output pins above the DTCLK pin on the right side of this block diagram is called [A BLOCK] and the output pins below the DTCLK pin
is called [B BLOCK].
MS1189-E-01
-2-
2010/12