AK8857VQ Datasheet, PDF (55/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Additionary, AK8857 supports “direct locking” mode that is not using VLOCK operation. (Direct SYNC
VLOCK)
VLOCKSEL-bit
[0]
[1]
Internal operation with the input signal frame structure
PLL SYNC VLOCK
Direct SYNC VLOCK
(Notice)
“Auto detection function” (Sub-Address0x0E[7]=1, 0x26[7]=1) must not use when it is being operated
on Direct SYNC VLOCK.
Auto Gain Control_AGC
The AGC of the AK8857 measures the size of the input sync signal (i.e., the difference between the
sync tip and pedestal levels), and adjusts the PGA value to bring the sync signal level to 286^a or 300^b
mV. The AGC function amplifies the input signal to the appropriate size and enables input to the AD
converter. The AGC function in the AK8857 is adaptive, and thus includes peak AGC as well as sync
AGC.
Peak AGC is effective for input signals in which the sync signal level is appropriate and only the active
video signal is large.
a _{NTSC-M, J; NTSC-4.43; PAL-M…………………………..286mV}
b _{PAL-B, D, G, H, I, N; PAL-Nc; PAL-60; SECAM…………300mV}
○AGCT[1:0]-bit : Settings for AGC time constant
AGCT[1:0]-bit Time constant
Notes
[00]
Disable
AGC OFF, PGA register enabled.
[01]
Fast
T= 1Field
[10]
Middle
T= 7Fields
[11]
Slow
T= 29Fields
T is the time constant.
Manual setting of the PGA register is possible only if AGC is disabled.
○AGCC-bit : Settings for AGC non-sensing range
AGCC[1:0]-bit
Non-sensing range
[00]
±2LSB
[01]
±3LSB
[10]
±4LSB
[11]
None
Notes
○AGCFRZ-bit : Settings for freezing AGC function
AGCFRZ-bit
AGC status
Notes
[0]
Non-frozen
[1]
Frozen
Note. The gain value at the time of freezing is maintained during the frozen state, and it is then
possible to read out the gain value via the PGA1,2 Control Register.
MS1189-E-01
-55-
2010/12