AK8857VQ Datasheet, PDF (59/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Clock
The AK8857 is operational by fixed-clock. To synchronized analog video signal, it doesn’t have PLL
internally. The input clock is 27Mhz. Only when progressive output of 720x487, VGA, WVGA output
format, the data is sampling to 54Mhz generated internally from the input clock 27Mhz.
Phase correction
In PAL-B, D, G, H, I, N, Nc, 60, and M decoding, the AK8857 performs phase correction for each line.
With this function ON, color averaging is performed for each line. In the adaptive phase correction
mode, interline phase correlation is sampled and color averaging is performed for correlated samples.
Interline color averaging is also performed in NTSC-M and J decoding.
No phase correction or color averaging is performed in SECAM decoding.
○DPAL[1:0]-bit : Settings for phase correction
DPAL[1:0]-bit
Status
[00]
Adaptive phase correction mode
[01]
Phase correction ON
[10]
Phase correction OFF
[11]
Reserved
Notes
Output interface
[1] Interface with EAV/SAV Sync
The EAV/SAV Sync code of ITU-R BT.656 standard interface can be added to the output data of
AK8857 when ITU-R BT.601 output size interlaced format is selected.
For the output size other than ITU-R BT.601 output size format, 2 pixels is added to the EAV/SAV
Sync code at the outside of DVALID signal active section. The changes also apply to V bit and Fbit
according to the lines where the polarity of VACT signal and FIELD signal is changed.
Relation between VACT and V bit
HD
HACT
DVALID
VACT
V bit
EAV SAV
EAV
Relation between FIELD and F bit
HD
DVALID
VD
FIELD
F bit
MS1189-E-01
EVEN
ODD
EAV SAV
-59-
ODD
EVEN
EAV SAV
2010/12