AK8857VQ Datasheet, PDF (76/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
AFE Control Register (R/W) [Sub Address 0x01] (Common Register)
Analog front end register setting.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x01
bit 7
bit 6
CLPWIDTH1 CLPWIDTH0
Default Value
0
0
bit 5
CLPSTAT1
0
bit 4
CLPSTAT0
0
bit 3
UDG1
Default Value : 0x01
bit 2 bit 1
bit 0
UDG0 CLPG1 CLPG0
0
0
0
1
AFE Control Register 1 Definition
Bit Register Name
R/W
Definition
Set the current value of fine clamp in analog
bit 0 CLPG 0
~~
bit 1 CLPG1
Clamp Gain
R/W
block
[00]: Min.
[01]: Middle 1 (Default)
[10]: Middle 2
[11]: Max
Set the current value of rough clamp in analog
bit 2 UDG 0
~~
bit 3 UDG 1
Up Down Gain
R/W
block.
[00]: Min. (Default)
[01]: Middle 1
[10]: Middle 2
[11]: Max
Set the position of clamp pulse
bit 4 CLPSTAT0
~
~
bit 5 CLPSTAT1
Clamp Start
R/W
[ CLPSTAT1 : CLPSTAT0 ]
[00] : Center of horizontal sync
[01] : (1/128) H delay
[10] : (2/128) H advance
[11] : (1/128) H advance
Set the width of clamp pulse.
bit 6 CLPWIDTH0
~
~
bit 7 CLPWIDTH1
Clamp Pulse Width
R/W
[ CLPWIDTH1 : CLPWIDTH0 ]
[00] : 296nsec
[01] : 593nsec
[10] : 1.1usec
[11] : 2.2usec
If the output of A block and B block is selected from the same channel of input video signal, the setting
of Sub-address0x01 [AFE Control Register] register only enable if REGSEL=[0] and disable if
REGSEL=[1].
During S-video signal decode, the output block register setting is enable if REGSEL=[0] and disable if
REGSEL=[1].
MS1189-E-01
-76-
2010/12