AK8857VQ Datasheet, PDF (81/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Pedestal Level Control Register (R/W) [Sub Address 0x06] (Common register)
Pedestal level adjustment setting register.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x06
bit 7
bit 6
DPCC1 DPCC0
Default Value
0
0
bit 5
DPCT1
0
bit 4
DPCT0
0
bit 3
BKLVL3
0
bit 2
BKLVL2
0
Default Value : 0x00
bit 1
bit 0
BKLVL1 BKLVL0
0
0
Pedestal Level Control Register Definition
Bit Register Name
bit 0 BKLVL0
~
~
bit 3 BKLVL3
Black Level
bit 4 DPCT0
~
~
bit 5 DPCT1
Digital Pedestal Clamp
Control
bit 6 DPCC0
~
~
bit 7 DPCC1
Digital Pedestal Clamp
Coring Control
R/W Definition
Setting for change from current pedestal
level by adding to or subtracting from black
level
[ BKLVL3 : BKLVL0 ]
[0001] : Add 1
[0010] : Add 2
[0011] : Add 3
[0100] : Add 4
[0101] : Add 5
R/W
[0110] : Add 6
[0111] : Add 7
[0000] : Default
[1000] : Subtract 8
[1001] : Subtract 7
[1010] : Subtract 6
[1011] : Subtract 5
[1100] : Subtract 4
[1101] : Subtract 3
[1110] : Subtract 2
[1111] : Subtract 1
Time-constant setting for digital pedestal
clamp
[ DPCT1 : DPCT0 ]
R/W [00] : Fast
[01] : Middle
[10] : Slow
[11] : Disable
Non-sensing bandwidth setting for digital
pedestal clamp
[ DPCC1 : DPCC0 ]
R/W [00] : ±1bit
[01] : ±2bit
[10] : ±3bit
[11] : No non-sensing band
MS1189-E-01
-81-
2010/12