AK8857VQ Datasheet, PDF (20/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Additionary, the AK8857 can change the position, width and current value of clamp pulse by registers.
○CLPWIDTH[1:0]: Set the width of clamp pulse.
CLPWIDTH[1:0]-bit
Clamp width
[00]
296nsec
[01]
593nsec
[10]
1.1usec
[11]
2.2usec
Notes
○CLPSTAT[1:0]: Set the position of clamp pulse.
CLPSTAT[1:0]-bit Clamp position
[00]
Sync tip/ middle/ bottom clamp: Centor of
horizontal sync
[01]
(1/128) H delay.
[10]
(2/128) H advance
[11]
(1/128) H advance
Notes
The positions of all clamp pulse are
changed.
Clamp Timing Pulse
CLPSTAT[1:0] = 00
CLPSTAT[1:0] = 01
CLPSTAT[1:0] = 11
CLPSTAT[1:0] = 10
CLPWIDTH[1:0]
1/128H delay
1/128H advance
2/128H advance
○CLPG[1:0] : Set the current value of fine clamp in analog block.
CLPG[1:0]-bit
Clamp current value
[00]
Min.
[01]
Middle 1 (Default)
[10]
Middle 2
[11]
Max.
Notes
Middle 1 = (Min. x 3)
Middle 2 = (Min. x 5)
Max. = (Min. x 7)
○UDG[1:0]: Set the current value of rough clamp in analog block.
UDG[1:0]-bit
Clamp current value
Notes
[00]
Min. (Default)
[01]
Middle 1
[10]
Middle 2
[11]
Max.
Middle 1 = (Min. x 2)
Middle 2 = (Min. x 3)
Max. = (Min. x 4)
Its digital circuit clamps the digitized input data to the pedestal level (digital pedestal clamp), and will
be described later.
MS1189-E-01
-20-
2010/12