AK8857VQ Datasheet, PDF (49/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Output Data format
In the AK8857, the settings for the output code and the vertical blanking intervals for the output signal
are as follows.
○601LIMIT-bit: Settings for output data code Min/Max
601LIMIT-bit
Output data code Min~Max
Notes
Y: 1~254
[0]
Cb, Cr: 1~254
Default
Y: 16~235
[1]
Cb, Cr: 16~240
All internal calculating operations are made with Min = 1, Max = 254.
With 601LIMIT-bit set to [1], codes 1~15 and 236~254 are respectively clipped to 16,235.
○TRSVSEL-bit: Settings for V-bit handling in ITU-R BT.656 format
TRSVSEL-bit
525-line
V-bit=0
V-bit=1
625-line
V-bit=0
V-bit=1
[0]
Line10~Line263 Line1~Line9
ITU-R BT 656-3
[1]
ITU-R BT 656-4
SMPTE125M
Line273~Line525
Line20~Line263
Line283~Line525
Line264~Line272
Line1~Line19
Line264~Line282
Line23~Line310
Line336~Line623
Line1~Line22
Line311~Line335
Line624~Line625
The TRSVSEL register only available during the interlace output decode by ITU-R BT.601 output size.
These values are unaffected by the VBIL[2:0]-bits setting.
○VBIL[2:0]-bit: Settings for vertical blanking interval
VBIL[2:0]-bit
Line Adjustment width
[000]
Default
[001]
1Line advance
2Line advance
[010]
2Lines advance
4Lines advance
[011]
3Lines advance
6Lines advance
[100]
4Lines advance
8Lines advance
[101]
5Lines advance
10Lines advance
[110]
6Lines advance
12Lines advance
[111]
7Lines advance
14Lines advance
*1: Other than progressive output
*2: Progressive output
Notes
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
*1
*2
The starting position of HACT signal and DVALID signal is changed according to VACT signal
starting position.
MS1189-E-01
-49-
2010/12