AK8857VQ Datasheet, PDF (85/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
PGA Control 1 Register (R/W) [Sub Address 0x0B]
PGA1 control register
In case of CVBS signal decode, its control the gain setting for A block output.
In case of S-Videosignal decode, its control the gain setting for Y signal output.
Sub Address 0x0B
bit 7
bit 6
PGA1_7
PGA1_6
Default Value
0
0
bit 5
PGA1_5
1
bit 4
PGA1_4
1
bit 3
PGA1_3
1
bit 2
PGA1_2
1
Default Value : 0x1F
bit 1
bit 0
PGA1_1 PGA1_0
1
0
PGA Control 1 Register Definition
Bit Register Name
bit 0 PGA1_0
~
~
bit 7 PGA1_7
PGA1 Gain Set
R/W Definition
R/W PGA gain setting, in steps of approx. 0.1 dB
*1 When CVBS signal decode, if the output of A block and B block is the same video signal, only
PGA1 control register is enable and PGA2 control register is disable.
*2 When CVBS signal decode, if the output block is selected to [non-decode], the gain setting is set
to “0x00” value.
PGA Control 2 Register (R/W) [Sub Address 0x0C]
PGA2 control register
In case of CVBS signal decode, its control the gain setting for B block output.
In case of S-Videosignal decode, its control the gain setting for C signal output.
Sub Address 0x0C
bit 7
Bit 6
PGA2_7
PGA2_6
Default Value
0
0
bit 5
PGA2_5
1
bit 4
PGA2_4
1
bit 3
PGA2_3
1
bit 2
PGA2_2
1
Default Value : 0x1F
bit 1
bit 0
PGA2_1 PGA2_0
1
0
PGA Control 2 Register Definition
Bit Register Name
R/W Definition
bit 0 PGA2_0
~
~
PGA2 Gain Set R/W PGA gain setting, in steps of approx. 0.1 dB
bit 7 PGA2_7
*1 When CVBS signal decode, if the output of A block and B block is the same video signal, only PGA1
control register is enable and PGA2 control register is disable.
*2 When CVBS signal decode, if the output block is selected to [non-decode], the gain setting is set to
“0x00” value.
MS1189-E-01
-85-
2010/12