AK8857VQ Datasheet, PDF (53/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
CLKINV-bit
A Block : CLKINV=[0]
B Block : CLKINV=[0]
A Block : CLKINV=[1]
B Block : CLKINV=[0]
A Block : CLKINV=[0]
B Block : CLKINV=[1]
A Block : CLKINV=[1]
B Block : CLKINV=[1]
A and B block at 27Mhz/54Mhz
output
DTCLK
DATA_A[7:0] D0 D1 D2 D3 D4
DATA_B[7:0] D0 D1 D2 D3 D4
DTCLK
DATA_A[7:0]
D0 D1 D2 D3
DATA_B[7:0] D0 D1 D2 D3 D4
DTCLK
DATA_A[7:0] D0 D1 D2 D3 D4
DATA_B[7:0]
D0 D1 D2 D3
DTCLK
DATA_A[7:0]
DATA_B[7:0]
D0 D1 D2 D3
D0 D1 D2 D3
A block : IP conversion output
DTCLK
DATA_A[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
DATA_B[7:0] D0 D1 D2 D3 D4
DTCLK
DATA_A[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8
DATA_B[7:0] D0 D1 D2 D3 D4
DTCLK
DATA_A[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
DATA_B[7:0] D0 D1 D2 D3 D4
DTCLK
DATA_A[7:0] D0 D1 D2 D3 D4 D5 D6 D7 D8
DATA_B[7:0] D0 D1 D2 D3 D4
Output data timing
The AK8857 can control timing of output data.
○YCDELAY[2:0]-bit: Adjustment of Y and C timing.
YCDELAY[2:0]-bit
Y and C timing
Notes
[001]
Y advance 1sample toward C.
2clk advance
[010]
Y advance 2 sample toward C.
4clk advance
[011]
Y advance 3 sample toward C.
6clk advance
[000]
No Delay and advance.
Default value
[101]
Y delay 3 sample toward C.
6clk delay
[110]
Y delay 2 sample toward C.
4clk delay
[111]
Y delay 1 sample toward C.
2clk delay
[100]
Reserved
*Setting by 2 complement
Because each sample is delay/advance toward C, 1sample is equall to 1clk width.
YCDELAY[2:0] = [000] ^{Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y5} Y/C default
YCDELAY[2:0] = [111] ^{Cb0 Y857 Cr0 Y0 Cb1 Y1 Cr1 Y2 Cb2 Y3 Cr2 Y4} _{1sample delay}
YCDELAY[2:0] = [001] ^{Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 Y4 Cb2 Y5 Cr2 Y6} 1sample adv.
DTCLK
MS1189-E-01
-53-
2010/12