AK8857VQ Datasheet, PDF (54/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
○ACTSTA[2:0]-bit: Adjustment of active video start position
ACTSTA[2:0]-bit
Line and active video start
Notes
[001]
525 Line Starting postion is delay 1 sample
2clk delay
[010]
525 Line Starting postion is delay 2 sample
4clk delay
[011]
525 Line Starting postion is delay 3 sample
6clk delay
[000]
525 Line Default value
Normal
position
[101]
525 Line Starting postion is advance 3 sample
6clk advance
[110]
525 Line Starting postion is advance 2 sample
4clk advance
[111]
525 Line Starting postion is advance 1 sample
2clk advance
[100]
Reserved Reserved
When the start position of active video is changed, the end position of active video also changed.
(Active video space is fixed)
ç ç Example : 720x487, 720x576(ITU-R BT.601)
Video Signal
HD
DVALID
HACT
ACTSTA[2:0]
=[000]
128CLK
244CLK
(264CLK)
DVALID
HACT
1440CLK
Active video section
32CLK
(24CLK)
ACTSTA[2:0]
=[001]
1sample
(2CLK)
1sample
(2CLK)
VLOCK mechanism
The AK8857 synchronizes internal operation with the input signal frame structure. If, for example,
the frame structure of the input signal comprises 524 lines, the internal operation will have a structure
of 524 lines per frame. This mechanism is termed the VLOCK mechanism. If an input signal
changes from a structure of 525 lines per frame to one of 524 lines per frame, internal operation will
change accordingly, and the VLOCK mechanism will go to UnLock via a pull-in process. In such case,
the UnLock status can be confirmed via the control register [VLOCK-bit]. Note that the time required
for locking of the VLOCK mechanism upon channel or other input signal switching will be about 2
frames. (PLL SYNC VLOCK)
MS1189-E-01
-54-
2010/12