AK8857VQ Datasheet, PDF (78/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Start and Delay Control Register (R/W) [Sub Address 0x03] (Common register)
Output data timing adjustment register.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x03
bit 7
bit 6
bit 5
bit 4
bit 3
VLOCKSEL ACTSTA2 ACTSTA1 ACTSTA0 Reserved
Default Value
0
0
0
0
0
Default Value : 0x00
bit 2
bit 1
bit 0
YCDELAY2 YCDELAY1 YCDELAY0
0
0
0
Start and Delay Control Register Definition
Bit Register Name
R/W
bit 0 YCDELAY0
~
~
bit 2 YCDELAY2
Y/C Delay Control R/W
bit 3 Reserved
Reserved
R/W
bit 4 ACTSTA0
~
~
bit 6 ACTSTA2
Active Video Start
R/W
Control
bit 7 VLOCKSEL
Vlock Select
R/W
Definition
Adjustment of Y and C timing.
[ YCDELAY2 : YCDELAY0 ]
[001] : Y advance 1sample toward C.
[010] : Y advance 2sample toward C.
[011] : Y advance 3sample toward C.
[000] : No Delay and advance.
[101] : Y delay 3 sample toward C.
[110] : Y delay 2 sample toward C.
[111] : Y delay 1 sample toward C.
[100] : Reserved
Reserved
Fine-tuning video data decode start position by
delay or advance in 1-sample units.
[ACTSTA2: ACTSTA0]
[001]: 1-sample delay
[010]: 2-sample delay
[011]: 3-sample delay
[000]: Normal start position
[101]: 3-sample advance
[110]: 2-sample advance
[111]: 1-sample advance
[100]: Reserved
Select of internal operation with the input signal
frame structure
[0]: PLL SYNC VLOCK
[1]: Direct SYNC VLOCK
MS1189-E-01
-78-
2010/12