AK8857VQ Datasheet, PDF (52/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Output pin status
For normal operation, the output from the DATA_A[7:0], HD_ACT_A, VD_ACT_A,
DVALID_A, FIELD_A, NSIG_A, DATA_B[7:0], HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B,
NSIG_B pins can each be fixed at Low via the Output Control Register.
The black level and blue level output have the priority to be output from the DATA_A[7:0] and
DATA_B[7:0] pins regardless of these register settings.
Note, however, that the OE_A, OE_B, PDN, RSTN pins and AINSEL[4:0] (non decode) states will
have priority regardless of these register settings.
Output pin timing signal
The timing signal can be output from the HD_ACT_A, VD_ACT_A, DVALID_A, FIELD_A,
HD_ACT_B, VD_ACT_B, DVALID_B, FIELD_B pins. The polarity of each timing signal at the output
pin can be invert by register setting.
At the HD_ACT output pin, the output signal can be selected between HD signal and HACT signal by
register setting.
At the VD_ACT output pin, the output signal can be selected between VD signal and VACT signal by
register setting.
○VDACTSEL-bit : VD/ VACT signal output setting
VDACTSEL-bit
VD_ACT output pin setting
[0]
VD signal is output
[1]
VACT signal is output
○HDACTSEL-bit : HD/ HACT signal output setting
HDACTSEL-bit
HD_ACT output pin setting
[0]
HD signal is output
[1]
HACT signal is output
The polarity of output from the DATA_A[7:0] / DATA_B[7:0] and DTCLKcan be inverted.
○CLKINV-bit: DTCLK signal polarity setting
CLKINV-bit
Polarity setting
[0]
Rising edge
[1]
Falling edge
If each of A or B output 54MHz, DTCLK pin output 54MHz. So, Not IP conversion data is alternated by
2CLK.
MS1189-E-01
-52-
2010/12