AK8857VQ Datasheet, PDF (15/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
(5) Power-down sequence and Reset sequence after power-down
Reset must be applied for at least 2048 clock cycles (or 83.33 µs) before setting PDN (PDN=Low).
Reset must be applied for at least 5 ms after PDN release (PDN=Hi).
CLKIN
RSTN
RESs
RESh
VIH
VIL
VIH
PDN
GND
Parameter
Reset width before setting PDN
Reset width after PDN release
Symbol
RESs
RESh
Min
2048
(75.85)
5
Typ
Max
Units
CLK
(usec)
msec
To perform power-down, all control signals must always be brought to the voltage polarity to be used or
to ground level.
For any power supply removal, all power supplies must be removed.
Clock input is necessary for resetting.
The power-down sequence for connection of the crystal is as follows.
AVDD/DVDD
PVDD1/PVDD2
PDN
RSTN
XTI
VCOM,VRP,VR
5 mS (max) to stable
crystal oscillator
REShʾ5mS(min)
PDN release
* Reference value
MS1189-E-01
-15-
2010/12