AK8857VQ Datasheet, PDF (88/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
NDMODE A Register (R/W) [Sub Address 0x0F] (A block register)
NDMODE B Register (R/W) [Sub Address 0x27] (B block register)
For limiting auto input video signal detection candidates of A block output data.
Sub Address 0x0F, 0x27
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Default Value: 0x00
bit 1
bit 0
ND625LA ND525LA NDPAL60A NDNT443A Reserved NDSECAMA NDPALNCA NDPALMA
ND625LB ND525LB NDPAL60B NDNT443B Reserved NDSECAMB NDPALNCB NDPALMB
Default Value
0
0
0
0
0
0
0
0
NDMODE A/B Register Definition
Bit Register Name
bit 0 NDPALMA/B
No Detect PAL-M_A/B
bit 1 NDPALNCA/B
No Detect PAL-Nc_A/B
bit 2 NDSECAMA/B No Detect SECAM_A/B
bit 3 Reserved
bit 4 NDNT443A/B
bit 5 NDPAL60A/B
Reserved
No Detect
NTSC-4.43_A/B
No Detect PAL-60_A/B
bit 6 ND525LA/B
No Detect 525Line_A/B
bit 7 ND625LA/B
No Detect 625Line_A/B
R/W Definition
[0] : PAL-M candidate
R/W
[1] : PAL-M non-candidate
[0] : PAL-Nc candidate
R/W
[1] : PAL-Nc non-candidate
[0] : SECAM candidate
R/W
[1] : SECAM non-candidate
R/W Reserved
[0] : NTSC-4.43 candidate
R/W
[1] : NTSC-4.43 non-candidate
[0] : PAL-60 candidate
R/W
[1] : PAL-60 non-candidate
[0] : 525 line candidate
R/W
[1] : 525 line non-candidate
[0] : 625 line candidate
R/W
[1] : 625 line non-candidate
In making the above register settings, the following restrictions are apply,
[1] Setting both NDNT443A/B (bit 4) and NDPAL60A/B (bit 5) to [1] (High) is prohibited.
[2] Setting both ND525LA/B (bit 6) and ND625LA/B (bit 7) to [1] (High) is prohibited.
[3] To limit candidate formats, it is necessary to have the auto detection mode OFF while first setting
the register to non-limited signal status and next the NDMODE settings, and then setting the auto
detection mode to ON.
MS1189-E-01
-88-
2010/12