AK8857VQ Datasheet, PDF (79/105 Pages) Asahi Kasei Microsystems – Dual Channel Digital Video Decoder

[AK8857VQ]
Control 1 Register (R/W) [Sub Address 0x04] (Common register)
Control register setting.
R/W block is depends on REGSEL setting of Sub-Address “0x00”.
Sub Address 0x04
bit 7
bit 6
Reserved EAVSAV
Default Value
0
0
bit 5
CLKINV
0
bit 4
bit 3
INTPOLOFF Reserved
0
0
Default Value: 0x00
bit 2
bit 1
bit 0
UVFILSEL YCSEP1
YCSEP0
0
0
0
Control 1 Register Definition
Bit Register Name
R/W
bit 0 YCSEP0
~
~
bit 1 YCSEP1
YC Separation
R/W
Control
bit 2 UVFILSEL
UV Filter Select
R/W
bit 3 Reserved
bit 4 INTPOLOFF
Reserved
R/W
Interpolator Mode
R/W
Select
bit 5 CLKINV
CLK Invert Set
R/W
bit 6 EAVSAV
bit 7 Reserved
EAV/ SAV SELECT R/W
Reserved
R/W
Definition
Y/C separation setting
[ YCSEP1 : YCSEP0 ]
[00] : Adaptive Y/C separation
[01] : 1-dimensional Y/C separation
[10] : 2-dimensional Y/C separation
[11] : Reserved
UV filter setting
[0]: Wide
[1]: Narrow
Reserved
Pixel interpolator setting
[0]: ON
[1]: OFF
DTCLK signal output polarity selection
[0] : Normal output
(write in data at rising edge)
[1] : Data and clock reversed
(write in data at falling edge)
EAV/SAV sync code add setting
[0]: Sync code is added
[1]: not added.
Reserved
MS1189-E-01
-79-
2010/12