GP1020 Datasheet, PDF (5/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

TIMING CHARACTERISTICS (See Figs. 4 to 9)
Characteristic
Symbol
Value
Units
Min. Max.
Address hold time
ALE pulse width
ALE valid to WEN or RW valid (WPROG = 1)
ALE valid to WEN or RW valid (WPROG = 0)
Address valid to ALE low
Address valid to WEN or RW valid
CS high to ALE valid
CS low to WEN or RW valid
Data hold time
Data setup time
RW high to data at high impedance
RW valid to data valid
RW valid to WEN high
WEN low to RW not valid
Write pulse width
CS hold time after RW or WEN not valid
t_AHOLD
10
t_ALEPW
20
t_ALESETUP
5
t_ALVWRV
20
t_ASETUP
20
t_AVWRV
20
t_CHALV
10
t_CVWRV
0
t_DHOLD
10
t_DSETUP
30
t_RHDZ
10
t_RVDV
10
t_RWVWENH
15
t_WENLRWNV
15
t_WLWH
30
t_WRCH
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25 ns
50 ns
ns
ns
ns
ns
NOTE. This timing information is based on simulations and is not verified by measurement on each device.
GP1020 BUS TIMING DIAGRAMS
GP1020
Conditions
WEN
CS
ALE
A (8:1)
D (15:0)
t_CVWRV
t_WRHCH
t_ALESETUP
t_WLWH
t_ALEPW
t_ASETUP
t_AHOLD
ADDRESS VALID
t_CHALV
NEXT
R/W
t_DSETUP
t_DHOLD
DATA VALID
RW
CS
ALE
A (8:1)
D (15:0)
t_CVWRV
t_WRHCH
t_ALESETUP
t_ALEPW
t_ASETUP
t_AHOLD
ADDRESS VALID
t_CHALV
NEXT
R/W
t_RVDV
t_RHDZ
DATA VALID
RW (HIGH)
Fig. 4 Intel 486 mode WRITE. MOT/INTEL = 0, WPROG = 1
(Write inhibited until ALE falling edge)
WEN (HIGH)
Fig. 5 Intel 486 mode READ. MOT/INTEL = 0, WPROG = 1
WEN
t_CVWRV
CS
t_WLWH
t_ALVWRV
ALE
t_AVWRV
A (8:1)
t_AHOLD
ADDRESS VALID
t_WRHCH
t_CHALV
NEXT
R/W
D (15:0)
t_DSETUP
t_DHOLD
DATA VALID
RW
t_CVWRV
CS
t_ALVWRV
ALE
A (8:1)
t_AVWRV
t_AHOLD
ADDRESS VALID
t_WRHCH
t_CHALV
NEXT
R/W
D (15:0)
t_RVDV
t_RHDZ
DATA VALID
RW (HIGH)
Fig. 6 Intel 186 mode WRITE. MOT/INTEL = 0, WPROG = 0
WEN (HIGH)
Fig. 7 Intel 186 mode READ. MOT/INTEL = 0, WPROG = 0
5