GP1020 Datasheet, PDF (28/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
RTC_INT
NEXT 2·275µs CLOCK EDGE
(FREE RUNNING)
TIC
PREVIOUS 2·275µs
CLOCK EDGE
TIME
UP TO 2·275µs DELAY
MAKES COUNT TOO HIGH
UP TO 2·275µs
DELAY MAKES
COUNT TOO
SMALL
Fig. 16
STAT_CHK_SEL Write Address C5_H
Register bit mapping
Description
Signal source
Bit
selection with the
following encoding:
Selected input port
Bit 3 2 1 0
3 to 0
0000
0001
0010
0011
0100
0101
0110
0111
1X00
1X01
1X10
1X11
0
1
2
3
4
5
6
7
8
9
Self test signal
Ground
15 to 4
Not used, don’t care.
REGISTER DESCRIPTION
STAT_CHK_SEL can be written into at any time. The SELF
TEST SIGNAL is both the sign and magnitude outputs (TSIGN
and TMAG output pins) of the SELF_TEST_GENERATOR
block and are connected internally.
STAT_CHK_SIGN and STAT_CHK_MAG
Read Addresses C5 and C6_H
Register bit mapping
non valid data will be latched in STAT_CHK_SIGN and
STAT_CHK_MAG registers. For this reason perform a dummy
read to STAT_CHK_MAG in order to clear the flag and wait for
the next time the flag is set to get valid data.
NOTE: the STAT_CHK_MAG register contains the number
of samples having the values 13 or23, and the STAT_CHK_SIGN
register contains the number of positive samples (1 or 3) from the
selected input port.
STATUS_LATCH WriteAddress 80_H
A write to this location with don’t care data latches the state
of all status bits contained in ACCUM_STATUS_A,
ACCUM_STATUS_B,
MEAS_STATUS_A
and
MEAS_STATUS_B. Performing a write to STATUS_LATCH
prior to reading the status registers ensures reading of stable
status values. The latch takes effect within 200 nanoseconds of
the leading edge of the write pulse. The LOW to HIGH transition
of the INT signal will also latch the state of the status bit, thus it
is not necessary to write to STATUS_LATCH when the status
registers are to be read as a response to the INT signal in an
interrupt handling routine. The write to STATUS_LATCH is
required only when the status registers are read at ‘random’
times, controlled by the microprocessor. These two mecha-
nisms are mutually exclusive and should not be used in conjunc-
tion - if they are both used (a write to STATUS_LATCH after the
occurance of an INT signal) contentions and confusion will result.
To avoid this, make sure a read access does not take
place at the same time as an interrupt rising edge.
If the INT_MASKB bit in TIMER_CNTL register is not set to
HIGH, the interrupt will not latch the status bits in the status
registers ACCUM_STATUS_A, ACCUM_STATUS_B,
MEAS_STATUS_A and MEAS_STATUS_B but a
STATUS_LATCH write access will do so. Also, when a GP1020
is configured as a slave, it should have the INT_SOURCE and
the INT_MASKB bits in the TIMER_CNTL register set to HIGH
to get the status bits sampled at the same instant in both master
and slave GP1020s.
Bit
Description
13 to 0
Unsigned integer ranging from 0 to 16383
representing the number of sign or
magnitude bits sampled during two
interrupt time base periods.
15 to 14
Don’t care, held LOW.
These registers are overwrite protected. The overwrite
protection is released and the NEW_STAT_DATA bit of the
ACCUM_STATUS_A is reset on the trailing edge of a read to
STAT_CHK_MAG or a write operation to ALL_ACCUM_RESET
location. Therefore, STAT_CHK_MAG should be read after
STAT_CHK_SIGN.
For the first time the flag NEW_STAT_DATA is set after a
master reset, if a write to the STAT_CHK_SEL register has not
been performed within two interrupt time base (INT) periods,
TDATA_DUTY_CYCLE Write Address C8_H
This register is associated with the
SELF_TEST_GENERATOR. It allows selection of the duty
cycle of the data inversion function.
The time base period is 11 C/A code chips. The value of
TDATA_DUTY_CYCLE, valid from 0 to 10, determines the
number of chips within the time base period where the data bit
modulating the self test signal will be inverted. When the self test
signal is fed back in a tracking channel, the inversion causes a
slope reversal in the accumulator of the Accumulate and Dump
module and prevents the accumulator from saturating over a
code epoch when TDATA_DUTY_CYCLE is properly set. This
is the same effect as noise on a real satellite signal.
REGISTER OPERATION
This register is a write only register and can be written into at
any time. At power up the register is reset, so it will always select
the data inversion function. If the bits are all 1 the data inversion
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