GP1020 Datasheet, PDF (25/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

CHx_TST_CODE_PHASE and
ALL_TST_CODE_PHASE
Write Addresses 06, 16, 26, 36, 46, 56 and 76_H
This location can be written into only if the CNTTESTMODE
signal, in the CHx_20MS_EPOCH is HIGH and if the MSB of the
CODE_DCO phase is LOW (power up condition). The
CHx_TST_CODE_PHASE is an unsigned 11 bit write only
register. It is used to pre-load the CODE_PHASE counter with
a specific value. ALL_TST_CODE_PHASE operates only on
those channels with CNTTESTMODE set high.
Register bit mapping
Bit
Description
10 to 0 11 bits of the CODE_PHASE counter
CHx_TST_CODE_SLEW
Read Addresses 01, 11, 21, 31, 41, 51_H
This location can be read at anytime for test purposes. It gives
access to actual contents of CHx_CODE_SLEW counter. It is
possible to read unstable data if the counter value is changing
during the read pulse.
Register bit mapping
Bit
Description
15 to 13 Don’t care
12
Bit 13 of CHx_CNTL register (test
purpose only)
11
Indicates the state of the CODE_SLEW
counter (for test purpose):
0: has reached the count of zero
1: counter value is not zero and/or the
counter is not enabled to count (see note)
10 to 0 Contents of CHx_CODE_SLEW
NOTE : the CODE_SLEW counter is enabled to count when it
has been loaded (CHx_CODE_SLEW register) and a DUMP
has occured if in Update mode. In Preset mode, the counter is
loaded and enabled to count upon a TIC event if the
CHx_20MS_EPOCH had been loaded.
CHx_TST_CYCLE and ALL_TST_CYCLE
Write Addresses 07, 17, 27, 37, 47, 57 and 77_H
This location can be written into only if the CNTTESTMODE
signal, in the CHx_20MS_EPOCH is active (HIGH) and if the
MSB of the CARRIER_DCO phase is LOW (as at power up). The
CHx_TST_CYCLE is an unsigned 16-bit write only register. It is
used to pre-load the CARRIER_CYCLE counter with a specific
value. The CARRIER_COUNTER is an 18-bit counter; the two
Less Significant Bits will be set to 0 when writing into
CHx_TST_CYCLE. ALL_TST_CYCLE operates only on those
channels whose CNTTESTMODE bit is High.
Register bit mapping
Bit
Description
15 to 0 16 MSB bits of the CARRIER_CYCLE counter
GP1020
CHx_1MS_EPOCH and ALL_1MS_EPOCH
Write Addresses A0, A4, A8, AC, B0, B4 and BC_H
These registers are write-only registers. Their operation is
affected by the current channel mode, PRESET or UPDATE. In
UPDATE mode, the data being written into these registers is
immediately transferred to the 1 ms epoch counter. In PRESET
mode however, the data is transferred only after the next TIC.
Refer to section 7 of DETAILED OPERATION OF THE GP1020
for more details of the PRESET mode.
Register bit mapping
Bit
Description
4 to 0
Contains the 1ms Epoch counter value to
be loaded. Its valid range is from 0 to 19.
15 to 5 Don’t care
CHx_20MS_EPOCH and ALL_20MS_EPOCH
Write Addresses A3, A7, AB, AF, B3, B7, and BF_H
These registers are write-only registers. Their operation is
affected by the current channel mode, PRESET or UPDATE. In
UPDATE mode, the data being written into 20MS_EPOCH is
immediately transferred to the 20 ms epoch counter. In PRESET
mode however, the data is transfered only after the next TIC. It
is important to load the 20MS_EPOCH register last in the
PRESET mode loading sequence because the trailing edge of a
write to this register enables the PRESET operation on the next
TIC. Refer to section 7 of DETAILED OPERATION OF THE
GP1020 for more details of the PRESET mode.
The CHx_20MS_EPOCH contains a test control bit
(CNTTESTMODE) which is used to test different counters in the
channels. When active this bit selects a 5·7 MHz clock (CLK 2)
to drive the 20MS_EPOCH counter and replace the CODECLK
signal by the TCK8 input signal, also TCK8 will drive the CODE
GENERATOR, the CODE_SLEW and CODE_PHASE counters,
and finally, it will allow the CODE GENERATOR to be set to the
1023rd chip position by a write operation to the
CHx_ACCUM_RESET location and to write into the
CHx_TST_CODE_PHASE and CHx_TST_CYCLE registers.
Register bit mapping
Bit
Description
15 to 7 Not used
6
CNTTESTMODE: Normal mode when LOW.
This bit is set LOW by a master reset and
should normally always be programmed LOW.
When HIGH, the CODE GENERATOR, the
20MS_EPOCH, CODE_PHASE, CODE_SLEW
and CARRIER_CYCLE counters are in test
mode.
5 to 0
Contains the 20 ms EPOCH counter value to
be loaded. Its valid range is from 0 to 49.
DOWN_COUNT_HI and DOWN_COUNT_LO
Write Addresses C3 and C4_H
These two registers are used to program the Time Mark
Generator. Refer to section 11 of DETAILED OPERATION OF
THE GP1020 (page 31) for more details of the principle of
operation of the Time Mark Generator.
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