GP1020 Datasheet, PDF (41/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
APPLICATION NOTES
PCB LAYOUT CONSIDERATIONS
The GP1020 is a fast CMOS device so, although clock rates are low, the edge speeds can be very high. The board layout must,
therefore, handle these edges on both output signals and on power supply current.
SIMPLIFIED SYSTEM
It is not always necessary to use all of the features of the GP1020 to make a good GPS receiver. The following pin connections
show the minimum requirement and are given as a guide only.
Unused inputs must be tied to V_SS or V_DD and not left floating. Failure to observe this may result in malfunction or damage to
the device.
Pin No.
Signal name
Description
Connection
1 and 2
3
4 and 5
6
7
8
9
10
11
12
13
14 and 15
16 and17
18
19
20
21
22
23 to 39
40
41
42 and 43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58 to 65
66
67
68 and 69
70
71
72 and 73
74
75
76 and 77
78 and 79
80
A7, A8
MASTER/SLAVE
TSCAN, TCKS
TDI1
MASTERRESET
MOT/INTEL
CS
V_SS
V_DD
WEN
RW
TMS2, TMS1
TMAG, TSIGN
MAG2
100/219kHz
V_DD
V_SS
INTOUT
SIGN and MAG 1 to 9
V_SS
V_DD
MAG0, SIGN0
SAMPCLK
V_DD
MASTERCLK
V_SS
BIAS
V_SS
V_DD
V_SS
CLKSEL
PLLLOCKIN
BITECNTL
GLONASSBIT
SLAVECLK
INTIN
TCK 1to 8
TICIN
TICOUT
D0 and D1
V_SS
V_DD
D2 and D3
TIMEMARK
RTCINT
MARKFB 1 and 2
D4 and D5
V_DD
Address bus
Master or Slave mode select
Control Test mode
Test Data serial input
General reset, active low
Bus mode select
Chip Select, active low
Ground
Positive supply
Write Enable - see mode table, page 3
Read/Write - see mode table, page 3
Test Mode Select 2 and 1
Test PRN pattern output
Source 2 MAG input
Clock output
Positive supply
Ground
Interrupt output
Source 1 to 9 SIGN and MAG inputs
Ground
Positive supply
Source Mag and SIGN inputs
Sampling clock
Positive supply
40MHz Master Clock
Ground
Bias for Master Clock
Ground
Positive supply
Ground
100kHz (high)/219kHz (low) select
PLL Status input
BITE control to Front-end
GLONASS BITE input
Master to Slave clock
Interrupt input for Slave
Test clocks or signals
TIC input to Slave
TIC output from Master
Data bus
Ground
Positive supply
Data bus
1 PPS output
Real Time Clock interrupt input
Time Mark driver feedback
Data bus
Positive supply
To microprocessor
High, unless Slave
Both low
Low
Power-on timer
High for Motorola, low for Intel
To microprocessor
0V
15V
To microprocessor
To microprocessor
Both low
Leave open
Low
Leave open
15V
0V
To microprocessor
All low
0V
15V
To GP1010
To GP1010
15V
To GP1010
0V
See Fig. 12 (page 8)
0V
15V
0V
High
Low or GP1010
Leave open
Low
Leave open
Low
All low
Low
Leave open
To microprocessor
0V
15V
To microprocessor
Leave open
Low
Both low
To microprocessor
15V
Continued…
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