GP1020 Datasheet, PDF (19/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
DATA
LOAD
TIC
ACCUMULATOR
CARRIER
OVERFLOW
DCO
EN
RESET
ACCUMULATOR
CYCLE UP
CLK
COUNTER
2
16
LATCH
CARR_CYCLE
REGISTER
LATCH
CARR_DCO_PHASE
REGISTER
ENABLE
DATA
BUS
Fig. 13 CHx_CARR_CYCLE block diagram
tens of kilohertz to allow for oscillator drift and Doppler compen-
sation. An 18 bit counter will cover up to 262,143 cycles, which
is more than adequate.
REGISTER CONTENTS RANGE
CHx_CARR_CYCLE is a 16 bit register, unsigned, and the
validity range of the data is 0 to 2¹⁶21.
CHx_CARR_CYCLE content is protected by the overwrite
protection mechanism of measurement data. Thus for an
overwrite to occur, either the associated
CHx_NEW_MEAS_DATA status bit has to be cleared or
CHx_CARR_CYCLE itself has to be read.
CHx_CARR_DCO_PHASE Read Addresses A2, A6,
AA, AE, B2, B6
Register bit mapping
Bit
Description
9 to 0
11 and 10
15 to 12
Most significant bits of CHx_CARR_DCO
phase accumulator. The weight of the
least significant bit is 2p/1024 radian. These
bits form an unsigned integer valid from
0 to 1023.
CHx_CARR_DCO_PHASE provides the
sub-cycle integrated phase measurement
information and therefore complements
the information given by CHx_CARR_CYCLE
Least significant bits of the number
of carrier DCO cycles that occurred during
the last TIC period ending at a TIC. The
value is sampled and latched on the TIC.
Not used.
CHx_CARR_INCR_HI & CHx_CARR_INCR_LO and
ALL_CARR_INCR_HI & ALL_CARR_INCR_LO
Write Addresses 04 & 05, 14 & 15, 24 & 25, 34 & 35,
44 & 45, 54 & 55 and 74 & 75_H
Register bit mapping
Bit
Description
CARR_INCR_HI
9 to 0
CARR_INCR_LO
15 to 0
More significant bits of the Carrier
DCO phase increment.
Less significant bits of the Carrier
DCO phase increment.
REGISTER OPERATION
The registers CARR_INCR_LO and CARR_INCR_HI are
combined to form the 26 bits of the CARR_INCR register, the
carrier DCO phase increment. Both registers are write-only
registers and can be written to at any time. The first write must be
performed on CARR_INCR_HI and the second write on
CARR_INCR_LO. The written value is latched in the CARR_INCR
register on the trailing edge of a write to CARR_INCR_LO. It is
possible to perform a write only to CARR_INCR_LO register if
the CARR_INCR_HI value does not need to be updated.
The DCO adder is 27 bits wide and the LSB of the INCR
register represents a step given by:
Min. Step Freq. = (40MHz/7)32²²⁷ = 42·57475 milliHertz
and the output frequency is:
Freq. out = CHx_CARR_INCR reg. value3Min. Step Freq.
The register value is latched on a TIC and protected from
overwrite by the overwrite protection mechanism of measure-
ment data.
The nominal value of the CHx_CARR_INCR register for GPS
is 01F7 B1B9_H (to get a carrier at 1·405396825 MHz when the
GP1010 clock signal is at 40 MHz).
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