GP1020 Datasheet, PDF (40/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
15. BOUNDARY SCAN LOOP
A boundary scan loop is implemented to allow the ATE to verify the connections of the chip at board level. The following pins are
not included in Boundary Scan Loop :
TDI1
PLLLOCKIN
MARKFB1
NANDOP
100/219kHz
SLAVECLK
MARKFB2
SAMPCLK
TCK(1:8)
MARKFB3
MASTERCLK
MARK
NANDA
BIAS
RTCINT
NANDB
The TAP controller has all functions necessary to be compatible with the JTAG standard (IEEE 1149.1-1990) with a few exceptions:
All bidirectional pins are in input mode when the TRST signal is inactive (HIGH)
so the chip cannot run freely when in bypass mode.
The Capture-IR state loads the instruction 000 instead of x01.
•_{The pins TMS, TCK and TRST do not have pull-up resistors.}
••_{This is the order of the pins in the loop (column by column):}
A7
A8
MASTER/SLAVE
TCKS
MASTERRESET
MOT/INTEL
CS
WEN
RW
TMS2
TMS1
TMAG*
TSIGN*
MAG2
INTOUT*
SIGN2
MAG3
SIGN3
MAG4
SIGN4
MAG5
SIGN5
MAG6
SIGN6
MAG7
SIGN7
MAG8
SIGN8
MAG9
SIGN9
MAG1
SIGN1
MAG0
SIGN0
CLKSEL
BITECNTL*
GLONASSBIT
INTIN
TICIN
TICOUT*
D0
D1
D2
D3
D4
D5
D6
D7
WPROG
D8
D9
D10
D11
D12
D13
D14
NOTE: An asterisk in the above list indicates an output pin.
D15
ALE
A1
A2
A3
A4
A5
A6
TSCAN
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