GP1020 Datasheet, PDF (26/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
DOWN_COUNT_LO is programmed with a 16-bit unsigned
integer word, with valid range from 0 to FFFF (HEX).
DOWN_COUNT_HI is programmed with a 5-bit unsigned
integer word, with valid range from 0 to 01F (HEX).
The concatenated value of both registers represents the time
delay, less 25 nanoseconds, from the next TIC to the Time Mark
output signal in units of 50 nanoseconds.
The trailing edge of a write to DOWN_COUNT_LO arms the
Time Mark Generator. When the next TIC occurs, the Time Mark
Counter is loaded and then decrements until it reaches zero, at
which instant the Time Mark is output.
MEAS_STATUS_A Read Addresses 80_H
Register bit mapping
Bit
Description
0
CH1_NEW_MEAS_DATA
1
CH2_NEW_MEAS_DATA
2
CH3_NEW_MEAS_DATA
3
CH4_NEW_MEAS_DATA
4
CH5_NEW_MEAS_DATA
5
CH6_NEW_MEAS_DATA
6
Not used
7
Not used
8
Not used
9
Not used
10
Not used
11
Not used
12
Not used
13
Not used
14
MARK_FB_ACK
15
RTC_TIC_ACK
REGISTER DESCRIPTION
MEAS_STATUS_A is located at an address contiguous with
accumulated data status registers so that it can be read in the
same read block operation. The status bits of this register are
sampled and latched on the positive edge of every INT OUT or
INT IN signal. They can also be sampled and latched on request
by performing a write operation to STATUS_LATCH location.
BIT DESCRIPTION
CHx_NEW_MEAS_DATA status bit active HIGH indicates if
there is new measurement data available to be read. Each
individual bit can be cleared by a write operation with don’t care
data to CHx_MEAS_RST. This operation releases the overwrite
protection. Each bit is also cleared on the trailing edge of a read
of the associated CHx_CARR_CYCLE register. If new accumu-
lated data becomes available after status bits have been latched,
the overwrite protection is not cleared while reading the
CHx_CARR_CYCLE register and the CHx_NEW_MEAS_DATA
bit will be set at the next MEAS_STATUS_A. A master reset
(hardware or software) and the inhibition of clock phases will also
clear this status bit.
RTC_TIC_ACK status bit is set whenever a Real Time Clock
interrupt has been received and the 100ms_TIC or 9ms_TIC
following the interrupt has occured. It is reset by a read of
RTC_DELAY register or an ALL_MEAS_RST command.
RTC_DELAY is overwrite protected by the measurement data
protection mechanism.
MARK_FB_ACK status bit is set whenever a Time Mark
feedback signal has been received on the selected pin,
MARK_FB1, MARK_FB2 or MARK_FB3 or by the selected edge
of the TIC OUT signal. It is reset by a read of PROP_DELAY_LO
register or a ALL_MEAS_RST command. MARK_FB_ACK is
overwrite protected by the measurement data protection mecha-
nism.
RTC_TIC_ACK and MARK_FB_ACK status bits are cleared
26
by a hardware master reset. A software master reset does not
affect the TIME BASE GENERATOR block, where these two
flags are generated.
MEAS_STATUS_B Read Address 81_H
Register bit mapping
Bit
Description
0
CH1_MISSED_MEAS
1
CH2_MISSED_MEAS
2
CH3_MISSED_MEAS
3
CH4_MISSED_MEAS
4
CH5_MISSED_MEAS
5
CH6_MISSED_MEAS
6
Not used
7
Not used
8
CH1_SLEW
9
CH2_SLEW
10
CH3_SLEW
11
CH4_SLEW
12
CH5_SLEW
13
CH6_SLEW
14
Not used
15
Not used
REGISTER DESCRIPTION
MEAS_STATUS_B register is located at an address contigu-
ous with accumulated data status registers so that it can be read
in the same read block operation. The status bits of this register
are sampled and latched on the positive edge of every INT OUT
or INT IN signal. They can also be sampled and latched on
request by performing a write operation to STATUS_LATCH
location.
BIT DESCRIPTION
CHx_MISSED_MEAS: status bit active HIGH indicating if
there has been missed measurement data resulting from a too
long delay (> TIC period) before the measurement data specific
to this channel was either read or the CHx_NEW_MEAS_DATA
bit was cleared. This bit is set on a TIC and latched until either
a master reset (hardware or software) or until a write operation
to CHx_MEAS_RST
CHx_SLEW: Status indicating if the code phase counter was
being slewed at time of TIC sampling. If such is the case, the
measurement data is not reliable. This bit is updated at each TIC
when the overwrite protection is not active and is reset whenever
CHx_MEAS_RST is written into with don’t care data or upon a
master reset (hardware or software).
All status bits in this register will also be cleared when the
clock phase propagation is disabled.
PROP_DELAY_LO and PROP_DELAY_HI
Read Addresses C3 and C4_H
Register bit mapping, PROP_DELAY_LO
Bit
Description
15 to 0 16 less significant bits of down counter
Register bit mapping, PROP_DELAY_HI
Bit
Description
4 to 0 5 more significant bits of down counter.
15 to 5 Don’t care, held LOW.