GP1020 Datasheet, PDF(36/44 Page) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

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GP1020 Datasheet, PDF (36/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

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GP1020

13. BUILT-IN TEST Functions

A. CHIP LEVEL Built-in Test Functions

SELF_TEST_GENERATOR

The GP1020 provides an on-chip self-test pattern generator

which is switched on under software control by setting

SELF_TEST_EN bit of the BITE register. It uses tracking chan-

nel 1 or 2 according to the setting of SELF_TEST_SOURCE bit

of the BITE register to generate SIGN and MAGNITUDE -like

signals which can be fed back to any or all other channels by

selecting the self test signal source in CHx_SIG_SEL. The self-

test signal has a fixed data bit pattern of alternating one and zero

every 20 milliseconds, the first bit being LOW. It has a fixed noise

pattern which corresponds to particular In-phase and Quad-

phase accumulated values. The C/A code and the Doppler shift

can be varied by programming the relevant registers of the

channel which has been selected by SELF_TEST_SOURCE.

The standard software can then be used to acquire and track the

self-test signal but it should take into account the fact that this

self-test signal is not a real GPS signal.

The SELF_TEST_GENERATOR output signal can also be

wrapped around externally by connecting the TSIGN and TMAG

output pins to a GPS or GLONASS input port. Normally, the test

source and tested channels will have the same DCO settings.

The next table contains the truth table of the weight converter

used in the SELF_TEST_GENERATOR :

CARRIER_DCO bits

(MSB-LSB)

MAG SIGN

01011

011xx

100xx

10100

All other combinations

MSB

The design of the weight converter will drive a HIGH on the

SIGN bit for 50% of the time and on the MAG bit for 31% of the

time.

Examples 1 and 2 show the results of the five first accumula-

tions of the accumulated data for two different settings of the

SELF_TEST_GENERATOR and the channels. Because the

channels had been started at the same time, they are practically

in phase with the incoming data (Sign and Mag outputs of the

SELF_TEST_GENERATOR).

Example 1:

Value

(Hex)

Comments

BITE

0020 STG on, CH1 as source

TDATA_DUTY_CYCLE

0000

No noise (will cause an overflow

condition in Q_PROMPT register

if signals are in phase)

CHx_SIG_SEL

CHx_CODE_INCR_HI

CHx_CODE_INCR_LO

CHx_CARR_INCR_HI

CHx_CARR_INCR_LO

CHx_CNTL

000A

016E

A4A8

01F5

C28F

0225

Signal from the STG

SV PRN 19, Dithering code

RESET_CNTL

007F Start all channels at the same time

Results

CHx_I_DITH

CHx_Q_DITH

CHx_I_PROMPT

CHx_Q_PROMPT

First

dump

0388

3D28

0A30

7FFC

Second

dump

0318

3D98

093C

7FFC

Third

dump

016C

3C34

0930

7FFC

Fourth

dump

04CC

3D78

08F8

7FFC

Fifth

dump

02AC

3FE4

0978

7FFC

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