GP1020 Datasheet, PDF (20/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
CHx_CODE_INCR_HI & CHx_CODE_INCR_LO and ALL_CODE_INCR_HI & ALL_CODE_INCR_LO
Write Addresses 02 & 03, 12 & 13, 22 & 23, 32 & 33, 42 & 43, 52 & 53 and 72 & 73_H
Register bit mapping
Bit
Description
CODE_INCR_HI
8 to 0
More significant bits of the Code DCO
phase increment.
CODE_INCR_LO
15 to 0
Less significant bits of the code DCO
phase increment.
CODE_INCR_LO. The written value is latched in the
CODE_INCR register on the trailing edge of a write to
CODE_INCR_LO. It is possible to perform a write only to
CODE_INCR_LO register if the CODE_INCR_HI value does
not need to be updated.
The DCO adder is 26 bits wide and the LSB of the INCR
register represents a step given by:
Min. Step Freq. = (40MHz/7)32²²⁶ = 85.14949 milliHertz
and the output Frequency is:
Freq. out = CHx_CODE_INCR reg. value3Min. Step Freq.
REGISTER OPERATION
The registers CODE_INCR_LO and CODE_INCR_HI are
combined to form the 25 bits of the CODE_INCR register, the
code DCO phase increment. Both registers are write-only
registers and can be written to at any time. The first write must
be performed on CODE_INCR_HI and the second write on
NOTE: The CODE DCO drives the CODE GENERATOR to
give half-chip time steps and so must be programmed to twice
the required chip rate. This means that the chip rate resolution
is 42·57475 milliHertz.
The nominal value of the CHx_CODE_INCR register for
GPS is 016E A4A8_H (to get a chip rate of 1.023MHz when the
GP1010 clock signal is at 40 MHz).
CHx_CNTL and ALL_CNTL Read/Write Addresses 00, 10, 20, 30, 40, 50, and 70 _H
Register bit mapping
Operation mode
Bit
of CHx_CNTL reg.
(Set by bit 15)
Description
7 to 0
9 to 0
MODE1
MODE2
C/A CODE SELECTION FUNCTION
(see details below)
9 and 8
MODE1
CODESEL(0:1):selects the apppropriate code to be shifted out of the
dithering arm output of the code generator as follows:
9 = 0 8 = 0 Early code
9 = 0 8 = 1 Late code
9 = 1 8 = 0 Dithering code
9 = 1 8 = 1 Early minus late code
10
MODE1&2
GLO/GPSB: Selects the code type to be generated. GLONASS C/A
code when HIGH, GPS or INMARSAT C/A code when LOW.
11
MODE1&2
CODE_OFF/ONB: When LOW, the code is output normally, but when
HIGH, the Prompt, Early and Late codes are held HIGH (no effect on the
mixer outputs) and the Early-minus-late code is held LOW to mask
mixer outputs and force I&D input values to 0.
12
MODE1&2
PRESET/UPDB: While HIGH, Programs the channel to Preset mode, or
while LOW, programs the channel to Update mode.
14 and 13
14 and 13
MODE1
MODE2
not used - don’t care
CODESEL(0:1) As bits 9 and 8 MODE1.
15
——
MODE: When LOW the CNTL register is in MODE1 (power up condition)
and when HIGH in MODE2. When in MODE1, the selection of a C/A
code is done by selecting two taps of the G2 register, but in MODE2
by presetting the value of the G2 register. The function of bits 8 and 9
will change depending on the MODE.
REGISTER OPERATION
CHx_CNTL can be written into at any time and any modifica-
tion to its content is effective immediately (within 250 ns) while
in UPDATE mode, or for all bits except PRESET/UPDB at the
next TIC while in PRESET mode. Before reading the content of
this register, it is necessary to wait 250 ns after the last write
operation when in UPDATE mode. Only the PRESET bit is
available immediately but it is cleared 150ns after the PRESET
sequence has taken place (at the TIC following the initialisation
of CHx_20MS_EPOCH register). It is important to program this
register first when starting a PRESET initialisation sequence.
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