GP1020 Datasheet, PDF (23/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

CHx_EPOCH_A
Read Addresses A0, A4, A8, AC, B0, B4_H
This register contains the variables as detailed below.
Register bit mapping
Bit
Description
15 to 11
CHx_1MS_EPOCH: The one millisecond
epoch counter value sampled at TIC
event. Its valid range is 0 to 19.
10 to 0
CHx_CODE_PHASE: Represents the
code phase of the code generator
when sampled and latched on a TIC,
expressed as a number of half code chips.
It ranges from 0 to 2045 when a GPS
C/A code is generated and from 0 to 1021
when a GLONASS C/A code is generated.
CHx_EPOCH_A content is protected from overwrite by the
overwrite protection mechanism of measurement data.
CHx_EPOCH_B
Read Addresses A1, A5, A9, AD, B1, B5_H
The register contains two variables as detailed below:
Register bit mapping
Bit
Description
15 and 14 Not used.
13 to 8
CHx_20MS_EPOCH: Contains the 20
millisecond epoch counter value sampled
at TIC event. Its valid range is from 0 to 49.
7 to 0
CHx_CODE_DCO_PHASE: Contains the
eight most significant bits of the code DCO
phase accumulator sampled at TIC event.
The weight of the least significant bit
is 2p/256 radians, 2p being 1/2 code
chip. The byte is an unsigned integer
valid from 0 to 255.
CHx_EPOCH_B content is protected from overwrite by the
overwrite protection mechanism of measurement data.
CHx_EPOCH_CHK
Read Addresses 02, 12, 22, 32, 42, 52_H
This register contains the instantaneous value of
CHx_1MS_EPOCH and CHx_20MS_EPOCH. It can be used to
verify if the Epoch counters have properly been initialised by the
software since the timing is critical for the initialisation operation.
Its value is not latched and is updated on the occurence of a
DUMP. This register should be read only when there is no
possibility of getting a DUMP during the read cycle.
Register bit mapping
Bit
Description
15 to 13
12 to 8
7
6
5 to 0
Not used.
Instantaneous value of CHx_1MS_EPOCH.
Bit 14 of CHx_CNTL (test purpose only)
CNTTESTMODE bit
Instantaneous value of CHx_20MS_EPOCH.
GP1020
CHx_I_DITH, CHx_Q_DITH, CHx_I_PROMPT,
CHx_Q_PROMPT
24 consecutive Read Addresses 84 to 9B_H
Register bit mapping
Bit
Description
15 to 2
Accumulated data registers, which are
loaded on each Dump event with the I&D
accumulator results.
1
Not used, held LOW.
0
Instantaneous value of the over/underflow
flag (for test purposes). Normally LOW,
but HIGH if the data being accumulated in
the I&D accumulator has reached the
over/underflow condition.
REGISTER OPERATION
These registers are read only registers; they can be read at
any time and their content is protected by the overwrite protection
mechanism of accumulated data. The CHx_I_PROMPT and
CHx_Q_PROMPT contain the accumulated data taken on the
Prompt arm. The CHx_I_DITH and CHx_Q_DITH contain the
accumulated data taken on the Dithering arm. The overwrite
protection mechanism is released by reading the
CHx_Q_PROMPT register.
The values contained in the registers are 2’s complement
values with the valid range of the data from 2¹³ for negative
numbers to (2¹³ 21) for positive numbers. When an over/
underflow condition is flagged (CHx_OVFL_ACCUM bit in
ACCUM_STATUS_B set HIGH) the contents of the registers for
this arm will be the last I&D accumulator values before the over/
underflow condition happened. If bit 15 is LOW it is an overflow
and if bit 15 is HIGH it is an underflow. Bits 0 of the 24
accumulated data registers have no link with the other data in
these registers. When HIGH, each of these bits indicates that the
data being accumulated in the I&D has reached the maximum
value (positive or negative) of the accumulator and this value will
be available at the next DUMP.
CHx_MEAS_RST and ALL_MEAS_RST
Write Addresses 84, 88, 8C, 90, 94, 98 and 9C_H
A write to this location with don’t care data resets all measure-
ment data status bits contained in both MEAS_STATUS_A and
MEAS_STATUS_B registers. It also clears any active overwrite
protection on measurement data. ALL_MEAS_RST access will
also clear the MARK_FB_ACK and the RTC_TIC_ACK flags in
MEAS_STATUS_A register and the associated overwrite pro-
tections.
CHx_PRESET_PHASE and ALL_PRESET_PHASE
Write Addresses A1, A5, A9, AD, B1, B5 and BD_H
Register bit mapping
Bit
Description
7 to 0
Most significant bits of the Code DCO
phase which is to be loaded at next TIC
event if in PRESET mode.
REGISTER OPERATION
In PRESET mode, the 8 bits of the PRESET_PHASE register
are added to the top 7 bits of the CHx_CODE_INCR register
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