GP1020 Datasheet, PDF (13/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
GP1020 REGISTER ADDRESSES AND CONTENT
Overall Memory Map
The GP1020 internal registers are addressed using 8 address lines, A1 to A8. This section gives an overview of the
register names with their addresses. A detailed memory map is shown in the Table of Registers.
Address range
(Hex)
Register Block accessed
00 to 07
Access to control registers of tracking channel 1
10 to 17
Access to control registers of tracking channel 2
20 to 27
Access to control registers of tracking channel 3
30 to 37
Access to control registers of tracking channel 4
40 to 47
Access to control registers of tracking channel 5
50 to 57
Access to control registers of tracking channel 6
70 to 77
For write operations only. Access to all identical control
registers of all tracking channels with one single operation.
The same data gets written in these registers.
80 to 83
Access to Accumulated Data and Measurement Data Status
84 to 9B
Access to In Phase and Quad Phase accumulated data registers
and SBR (Status Bit Reset) commands of all tracking channels.
9C,9D
Access to all identical SBR (Status Bit Reset) commands of all
tracking channels with a single write operation.
A0 to B7
Access to measurement data registers of all tracking channels.
BC to BF
For write operations only. Access to all identical measurement
data registers of all tracking channels with one single
operation. The same data gets written in these registers.
C0 to C8
Access to BITE interface, TIME_BASE_GEN, RESET_CNTL,
signal selector and test registers.
Other addresses not used. Do not access these addresses.
Note 1: Registers are not all READ/WRITE. To minimise the hardware, some addresses are shared between read-only and write-only
registers having different functions. Refer to TABLE OF REGISTERS for more details.
TABLE OF REGISTERS
Address
(Hex)
Register
Read function
Write function
00
CH1_CNTL
CH1_CNTL
01
CH1_TST_CODE_SLEW
CH1_SIG_SEL
02
CH1_EPOCH_CHK
CH1_CODE_INCR_HI
03
CH1_SHIFT_REG
CH1_CODE_INCR_LO
04
not used
CH1_CARR_INCR_HI
05
not used
CH1_CARR_INCR_LO
06
not used
CH1_TST_CODE_PHASE
07
not used
CH1_TST_CYCLE
08
not used
not used
09
not used
not used
0A
not used
not used
0B
not used
not used
0C
not used
not used
0D
not used
not used
0E
not used
not used
0F
not used
not used
10
CH2_CNTL
CH2_CNTL
11
CH2_TST_CODE_SLEW
CH2_SIG_SEL
Continued...
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