GP1020 Datasheet, PDF (31/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

DETAILED OPERATION OF THE GP1020
1. MASTER RESET - Hardware or Software.
At Master Reset, all registers, accumulators and counters are
cleared except CHx_CNTL. In particular, this implies the follow-
ing initial states:
• ^{All CHx_RSTB bits of the RESET_CNTL register are cleared.}
Thus all tracking channel clock phases are disabled. Program-
ming registers can take place either before or after releasing the
CHx_RSTB bits.
• ^{All the tracking channels are in UPDATE mode, the satellite}
code selected is GPS PRN No. 17 and the EARLY code is
selected on the dithering arm. All CHx_CNTL registers are in
•MODE 1.
The TIC generator will be free running at start-up with a
100ms TIC period setting. The INT_MASKB bit of the
TIMER_CNTL register is LOW, therefore the INT_OUT signal
will be disabled and the output pin held LOW. The interrupt time
•base is set to 505.05µs.
The BITECNTL bit of the BITE register is reset LOW (inactive
state). The associated BITECNTL output pin is also LOW.
• ^{The data bus is forced into input mode to avoid contention at}
power up.
2. SEARCH OPERATION at Power up, after a power
glitch, or after losing satellite signals.
REGISTER INITIALISATION
For each channel, the proper GPS or GLONASS signal
source has to be selected by writing the proper code into
CHx_SIG_SEL registers. The contents of these registers can be
changed at any time during the operation to change the signal
sources for any channels.
At power up, all CHx_RSTB bits of the RST_CNTL register
are in the reset LOW state. As stated above, in that state, all
tracking channel control registers can be programmed.
When it is required to perform a SEARCH for one satellite with
more than one channel, these channels are first reset if not
already in that state, with the corresponding CHx_RSTB bits,
then the control registers are programmed. In particular, each
CODE_SLEW register is programmed with a different value.
Then, the CHx_RSTB bits are released, causing the channels to
start operating at the same time with the same code phase. One
millisecond later, all channels will get the same accumulated
data and will be slewed with the pre-programmed values and will
continue with a known relative code phase difference. Note that
every time CHx_RSTB is set LOW, the code generator is reset.
The following additional initialisation operations have to be
performed. The block write addresses can be used whenever
appropriate.
CARRIER_DCO PROGRAMMING
The CARR_INCR_HI and the CARR_INCR_LO registers are
programmed in sequence with the relevant data according to the
estimated DOPPLER shift for the frequency bin being looked at.
The programming is effective as soon as the write operation to
CARR_INCR_LO is completed (In fact, a small delay of 175 ns
maximum will occur to allow synchronisation of the processor
write operation to the chip operation). If the content of
CARR_INCR_HI does not need to be modified, it is not neces-
sary to write into it. It is always necessary to write into
CARR_INCR_LO in order for the programming to be effective.
Note that, typically, the search algorithm would dwell on a given
frequency bin and perform a search over all code phases. Then
it would repeat the process for the next frequency bin.
CODE_DCO PROGRAMMING
The tracking channel being in UPDATE mode, the
PRESET_PHASE register does not need to be programmed.
The CODE_INCR_HI and the CODE_INCR_LO registers are
GP1020
programmed in sequence with the relevant data according to the
estimated DOPPLER shift. Given that the CHx_RSTB bit of the
RESET_CNTL register is inactive, the programming is effective
as soon as the write operation to CODE_INCR_LO is completed.
If the content of CODE_INCR_HI does not need to be modified,
it is not necessary to write into it. It is always necessary to write
into CODE_INCR_LO in order for the programming to be effec-
tive.
CODE GENERATOR PROGRAMMING
1. Select in CHx_CNTL register the type of code to be used in
the dithering arm of the correlator; normally, for a search opera-
tion, either an early or a late code is selected. The PRESET/
UPDB bit will be set LOW, for example, in UPDATE mode by
master reset.
2. Select in CHx_CNTL register the code to be generated among
the 45 possible C/A codes or the unique GLONASS code.
(Actually, all possible code combinations are programmable
even those not used by the GPS constellation and some
GLONASS-like codes are also available.) The selected code is
applicable to both the prompt and the dithering arm.
3. Program each tracking channel CODE_SLEW register with
the desired code phase. The slew operation will become effec-
tive at the first dump e.g. about 1 ms after CHx_RSTB release.
The first dump will generate don’t care accumulated data and will
set the associated CHx_NEW_ACCUM_DATA status bit. The
second and the following dumps will generate useful data.
4. Release the relevant CHx_RSTB bits of the RESET_CNTL
register in order to start operation of the tracking channels. When
channels of more than one GP1020 are being used to search for
the same code, consecutive write operations to each chip’s
RESET_CNTL register should ensure a startup with reasonably
well known relative code phases between the two chips.
Whenever the code clock is being inhibited (to slew the code
phase), the Accumulate & Dump module is held reset. It will start
to accumulate correlation results only after the slew operation is
completed.
3. READING the ACCUMULATED Data
Every time a DUMP occurs, the corresponding
CHx_NEW_ACCUM_DATA status bit is set in the
ACCUM_STATUS_A register. All In-phase and Quad-phase
registers together with ACCUM_STATUS_A and
ACCUM_STATUS_B registers are mapped in consecutive ad-
dresses so that they can be block-read after every timebase
interrupt. Alternatively, a polling technique can be used by
periodically reading the ACCUM_STATUS_A register to find if
an interrupt or a write into STATUS_LATCH has been per-
formed.
The data contained in the IN_PHASE and QUAD_PHASE
registers of the prompt and dithering arms will be protected from
an overwrite due to consecutive DUMP events. The protection
mechanism is released on the trailing edge of a read operation
of the Q_PROMPT register. Thus the order of reading I_DITH,
Q_DITH and I_PROMPT is optional but Q_PROMPT must
always be read last to ensure coherence of the data set and to
release the overwrite protection mechanism.
The CHx_MISSED_ACCUM bit of the ACCUM_STATUS_B
register indicates new accumulated data has been missed
because of a too long response time for reading the accumulated
data. This status bit, when set, is latched until it is cleared by a
write operation to CHx_ACCUM_RESET or by a master reset or
by CHx_RSTB set to LOW.
4. SEARCH on other CODE PHASES
When it is desired to correlate on the next code phase, the
CODE_SLEW has to be programmed with a value of 2 (in units
31