GP1020 Datasheet, PDF (35/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

UTC ERROR BUDGET
The following error budget is associated with the generation
of the Time Mark:
Total Error =
TDOP1Clock Resolution1Oscillator Drift Residual Error.
1 Computation induced Error.
1 Time mark transfer delay through Drivers/cables.
1 Propagation delay in hardware, from antenna to
correlator to measurement data sampler, where
typical values are:
1. TDOP: estimated at 177ns with S/A ON (2 s number)
2. Clock Resolution: 50ns (in 21 bit programmable down
counter).
3. Oscillator Drift Residual Error:
(a) Due to temperature change on
TCXO since last oscillator drift
computation: about 50ns, computed
with the following assumptions:
(i) TCXO max slope is ± 1 ppm/°C
(ii) Temperature max variation is 5 °C/minute
(iii) The oscillator drift is computed every
second and is at most one second old at UTC
time mark.
For example:
1ppm/°C 3 5°C/min 3 1sec
= 83ns for a temperature step change
or 41.5 ns (rounded to 50ns) for a linear ramp
(b) Due to bias in drift estimation about 50ns max (rough
guess)
TOTAL oscillator drift error = (a) 1 (b) ≈ 100ns.
GP1020
4. Computation induced error: It is assumed that enough
significant bits are retained such that this error approximates
zero.
5. TIME MARK transfer delay through drivers/cables: This
will be calibrated and compensated for up to the GPS receiver’s
output using the feedback to the down counter. There will be a
residual error due to:
(a) Clock resolution = 50ns
(b) Feedback delay calibration = 25ns (estimated)
6. Propagation delays in the hardware: These are estimated
to be in the range of a few microseconds and are therefore the
major contributor to the TIME MARK synchronisation error. An
estimate could be included in the software to improve total
accuracy when the total hardware design is complete.
TOTAL = 177ns150ns1100ns10175ns1hardware delays
TOTAL = 402ns1hardware delays.
12. INTEGRATED CARRIER PHASE measurement
The GP1020 tracking channel hardware allows measure-
ment of integrated carrier phase through CHx_CARR_CYCLE
and CHx_CARR_DCO_PHASE registers. These two registers
are part of the measurement data sampled every TIC. The first
one contains the 16 more significant bits of the number of full
cycles elapsed and the second one contains the two remaining
less significant bits plus the cycle fraction (phase). Fig. 22 shows
how to add consecutive readings of these registers over several
TICs in order to get a consistent integrated carrier phase.
CARRIER CYCLES MEASUREMENT
OVER MORE THAN ONE TIC PERIOD
TIC0
TIC1
TIC2
Y0
2p2Y0
Y1
K1 CYCLES
DY1
Y2
K2 CYCLES
DY2
1. Reading at TIC₀: CHx_CARR_DCO_PHASE₀ = Y₀
CHx_CARR_CYCLE₀ CLEARED
2. Reading at TIC₁: CHx_CARR_DCO_PHASE₁ =Y₁
CHx_CARR_CYCLE₁ = K₁11
DY₁ = 2p(K₁11) 1Y₁2Y₀
= 2p (CHx_CARR_CYCLE₁)1CHx_CARR_DCO_PHASE₁
2CHx_CARR_DCO_PHASE₀
3. Reading at TIC₂: CHx_CARR_DCO_PHASE₂ = Y₂
CHx_CARR_CYCLE₂ = K₂11
SDY = 2pS (CHx_CARR_CYCLE)1CHx_CARR_DCO_PHASE_LAST
2CHx_CARR_DCO_PHASE₀
Fig. 22 Integrated carrier phase measurement
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