GP1020 Datasheet, PDF (24/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
and the sum is loaded into the 8 bits of the CODE_DCO accumulator
along with all zeros in the lower bits. The PRESET_PHASE register
is a write only register and it can be written to at any time in PRESET
mode or in UPDATE mode. The weight of the least significant bit of
PRESET phase is 2p/256 radian of a half chip cycle.
CHx_SHIFT_REG
Read Addresses 03, 13, 23, 33, 43, 53_H
Register bit mapping
Bit
Description
15 to 13 Not used; don’t care data
12
Bit 15 (MODE bit) of CHx_CNTL (test
purpose only)
11
11th chip
10
12th chip
9
First chip
0
10th chip
REGISTER OPERATION
This register is used for test purpose only. The 12 less
significant bits of the word contain the first 12-bit sequence of the
C/A code issued by the channel’s code generator on the dither-
ing arm. The latching process is armed as a result of a completed
slew operation, a PRESET sequence or a clock phase release
by CHx_RSTB bit of the RESET_CNTL register. It is necessary
to wait at least 24 Code DCO clock cycles (12 µs in GPS mode
and 24 µs in GLONASS mode) before reading this register. The
3 most significant bits of the word are don’t care data. When in
Early Minus Late mode, this register will contain the first 12-bit
sequence of the code sign issued on the dithering arm.
The following table contains the result of the SHIFT_REG
register for all possible cases.
GPS/
GLONASS
C/A code
SHIFT_REG value
EARLY/LATE EARLY-MINUS-LATE
code
code
1
F20_H
2
F90_H
3
FC8_H
4
FE4_H
5
25B_H
6
32D_H
7
E59_H
8
72C_H
9
B96_H
10
B44_H
11
FA2_H
12
7E8_H
13
BF4_H
14
FFA_H
15
FFD_H
16
7FE_H
17
26E_H
18
B37_H
19
79B_H
20
3CD_H
21
3E6_H
640_H
A40_H
241_H
242_H
249_H
24A_H
248_H
648_H
A4A_H
689_H
289_H
A82_H
294_H
290_H
609_H
229_H
222_H
221_H
225_H
228_H
620_H
24
GPS/
GLONASS
C/A code
SHIFT_REG value
EARLY/LATE EARLY-MINUS-LATE
code
code
22
23
24
25
26
27
28
29
30
31
32
33
34 *
35
36
37 *
201
202
205
206
207
208
209
211
GLONASS
GLONASS
_TEST
BF3_H
E33_H
7F6_H
FE3_H
7F1_H
3F8_H
BFC_H
A57_H
72B_H
395_H
3CA_H
BE5_H
7CB_H
25C_H
B2E_H
7CB_H
BB9_H
35E_H
A70_H
3C1_H
A0B_H
630_H
AA5_H
71E_H
3F8_H
FF8_H
A12_H
610_H
249_H
205_H
621_H
608_H
242_H
A50_H
A52_H
254_H
250_H
649_H
648_H
244_H
245_H
648_H
222_H
684_H
A10_H
208_H
A08_H
610_H
AA4_H
A04_H
201_H
610_H
* Note C/A Codes 34 and 37 are the same.
CHx_SIG_SEL and ALL_SIG_SEL
Write Addresses 01, 11, 21, 31, 41, 51 and 71_H
Register bit mapping
Description
Signal source
Bit
selection with the
following encoding:
Selected input port
Bit 3 2 1 0
3 to 0
0000
0001
0010
0011
0100
0101
0110
0111
1x00
1x01
1x10
1x11
0
1
2
3
4
5
6
7
8
9
Self test signal
Ground
15 to 4
Not used, don’t care.
REGISTER DESCRIPTION
CHx_SIG_SEL can be written into at any time. The SELF
TEST SIGNAL is the sign and mag outputs (TSIGN and TMAG
output pins) of the SELF_TEST_GENERATOR block and are
wrapped round internally.