GP1020 Datasheet, PDF (37/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

Register settings
BITE
TDATA_DUTY_CYCLE
CHx_SIG_SEL
CHx_CODE_INCR_HI
CHx_CODE_INCR_LO
CHx_CARR_INCR_HI
CHx_CARR_INCR_LO
CHx_CNTL
RESET_CNTL
Example 2:
Value
(Hex)
Comments
0020 STG on, CH1 as source
07F7 Invert the data 8 times in 11
000A
016E
A4A8
01F5
B1B3
0315
Signal from the STG
SV PRN 1, Early_Minus_Late code
007F Start all channels at the same time
GP1020
Results
CHx_I_DITH
CHx_Q_DITH
CHx_I_PROMPT
CHx_Q_PROMPT
First
dump
2230
0598
F8F4
46D8
Second
dump
1EB8
0568
0078
4798
Third
dump
2170
0374
03E8
4914
Fourth
dump
2030
078C
FF08
47B8
Fifth
dump
1F00
03CC
0590
46D4
ADD_DAT_TST REGISTER
The ADD_DAT_TST register allows the software and the ATE
to verify the functionality of the data and address busses. For full
details see ADD_DAT_TST section of DETAILED DESCRIP-
TION OF REGISTERS.
B. SYSTEM-LEVEL Built-in Test Functions
GP1010 BITE interface:
The GP1020 BITE CNTL discrete output is provided to drive
the corresponding discrete input pin of the GP1010. When active,
this control unlocks the PLL and switches off the GP1010 front-
end amplifiers. As a result, the GP1020 should read an unlocked
status at its PLL LOCK discrete input.
The GP1020 includes Sign and Magnitude statistics checker
circuit.
GLONASS IC BITE interface:
Uses the same BITE CNTL discrete output to put the GLONASS
IC into test mode and one GP1020 discrete input pin,
GLONASSBIT, for GLONASS IC go/nogo status.
TIME MARK :
Three MARK FEEDBACK input pins, selected by bits 7 to 5 of
TIMER_CNTL, are provided for testing the signal outputs of
TIME MARK line drivers.
Also, software selectable control bits (TIMER_CNTL bits 4
and 8) allow multiplexing of the normal 1 second period TIME
MARK with one of two test signals, either 40MHz/91 =
439.5604KHz intended for oscillator drift measurement or
CH1_DUMP for system fault-finding purposes.
14. CHIP MANUFACTURING-TEST Functions
The GP1020 design incorporates a series of features to
increase (a) the observability of internal nodes when working in
the application and ( b) the observability and the controllability of
the circuit during chip-level testing during manufacture. The
following presents a summary of the chip test functions:
TEST REGISTERS
A number of registers have been added to improve the
testability of the chip. They are not required for normal
operation : CHx_TST_CODE_PHASE, CHx_TST_CYCLE and
CHx_TST_CODE_SLEW.
Scan Loops and Internal Node Real-Time Observability
A number of registers are not connected to the data bus in any
way. These registers have two modes of operation: The normal
mode and the SCAN LOOP mode in which the flip flops are cascaded
to form a shift register. There is one such scan loop per channel.
Fig. 23 shows a block diagram of the Chip test functions. TDI1
(Test Data In) is a serial input common to all scan loop shift registers.
Each scan loop has a separate data O/P pin TDO (1:7) (Test Data
Out).
The control signal TSCAN (Test Scan) determines whether the
registers operate in normal mode (TSCAN LOW) or in scan loop
mode (TSCAN HIGH).
The Control Signal TCKS (Test Clock Select), when HIGH,
selects the 7 test clocks TCK(1:7) as a replacement for the seven
clock phases provided by the clock generator in normal mode. This
is intended for use only in the device factory and not in normal
operational use. TMS1 and TMS2 are Test Mode Select control pins.
Their function is detailed in the following table:
TMS2 TMS1
LOW
LOW
HIGH
LOW
HIGH
X
Normal mode: SIGN (2:8) and
MAG (2:9) configured as inputs.
TDO (1:7) held LOW. TCK(1:7)
configured as inputs. SIGN (9) is
always used as a normal input.
Scan Loop mode: SIGN (2:8)
and MAG (2:9) onfigured as
inputs. TDO (1:7) output serial
scan data. TCK (1:7) configured
as inputs.
Channel 1 observability mode:
SIGN (2:8), MAG (2:9) and TCK
(1:7) configured as outputs and
together with TDO (1:7) allow
real-time observability of internal
nodes of channel 1 as listed
below. The internal TIC signal
and the signal latching the status
bits are also available on TDO4
and TDO7 pins.
37