GP1020 Datasheet, PDF (22/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
Bit
State
Description
7 to 0
9 and 8
03_H GPS PRN No. 17 selected.
00
Early Code on the dithering arm.
10
0
11
0
12
0
14 and 13 00
15
0
GPS C/A CODE
CODE ON
UPDATE MODE
N/A (MODE1)
MODE1
CHx_CODE_SLEW and ALL_CODE_SLEW Write Addresses A2, A6, AA, AE, B2, B6 and BE_H
Register bit mapping
Bit
Description
10 to 0
Unsigned integer ranging from 0 to 2047
representing the number of code half chips to
be slewed after the next DUMP if in
UPDATE MODE or after the next TIC, if in
PRESET MODE. Since there are only 2046
half chips in a GPS C/A code, a
programmed value of 2047 is equivalent to
a programmed value of 1 but the next DUMP
event will take place 1 ms later.
For the GLONASS code a similar wrap-
around will occur at 1023 and 2045.
The CHx_CODE_SLEW register can be written to at any
time. If two accesses have taken place before a DUMP in
UPDATE mode or before a TIC when in PRESET mode, the
latest value will be used at the next slew operation.
When the slew process is being executed, a write access
to the CHx_CODE_SLEW register will cause the transfer of
this new value into the counter and will be used immediately.
The result is not predictable. This situation should be avoided
by synchronising the access with the associated
CHx_NEW_ACCUM_DATA status bit.
Slew timing details are shown in Figs. 14 and 15.
1023 CHIPS
1025 CHIPS
DUMP:
t₁
TIME
C/A CODE CHIP NO. : 1021 1022 1023 1 1 1 2 3
t1: Load 4 in the CHx_CODE_SLEW register = 2 chips delay.
Fig. 14 SLEW in UPDATE mode
1023 CHIPS
1024·5 CHIPS
DUMP:
t₁ t₂
t₃
TIME
C/A CODE CHIP NO. :
98 99 100 1 1 1 2 3 4
t1: Set the PRESET mode (Bit 12 in CHx_CNTL register)
t2: Load 3 in the CHx_CODE_SLEW register (=1·5 chips delay)
t3: TIC event
Fig. 15 SLEW in PRESET mode
22