GP1020 Datasheet, PDF (18/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
When a write is performed at address C7_H the register will be
loaded with the data bus value present on the bus.
When a read operation is performed to C7_H it reads all the bits
previously loaded.
It is recommended that the test is performed as follows in
order to verify that the address and data bus operate properly.
Address Bus Test:
• ^{Write to address 55}H ^{(the data bits are don’t care)}
• ^{Read the most significant bits at address C7}H ^{(the 8 least}
significant bits are 00_H if no access had been done to the
address C7_H). If the value is not 5500_H a problem is
detected on the address bus.
• ^{Write to address AA}H ^{(the data bits are don’t care)}
• ^{Read the most significant bits at address C7}H^{. If the value}
is not AA00_H a problem is detected on the address bus.
NOTE : When writing to addresses 55_H and AA_H, the
CH6_CARR_INCR_LO and CH3_CODE_SLEW registers
will also be written into with the values on the data bus.
Data Bus Test:
• ^{Write 5555}H ^{to address C7}H
• ^{Read the register at address C7}H^{. If the value is not 5555}H
a problem is detected on the data bus.
• ^{Write AAAA}H ^{to address C7}H
• ^{Read the register at address C7}H^{. If the value is not AAAA}H
a problem is detected on the data bus.
BITE Read/Write Address C1 _H
Register bit mapping
Bit
Description
0
BITECNTL
1
DISCOP
2
PLL_LOCKA (state)
3
PLL_LOCKB (negative transition)
4
GLONASS BIT
5
SELF_TEST_EN
6
SELF_TEST_SOURCE
7
MEANDER
8
CARR_MIX_ENB
BIT DESCRIPTION
BITECNTL bit: Drives the BITE input of the GP1010. Set
inactive LOW by a Master Reset. When HIGH, the
GP1010’s PLL is unlocked and the 40 MHz signal be-
comes unstable. The GP1020 should be put into hardware
master reset mode for the time needed to allow the
GP1010’s 40 MHz output to stabilise.
DISC O/P: Discrete output with no specific function. LOW
at power up and its state will follow the value written in the
BITE register.
PLL_LOCKA: input from GP1010, Read only, to indicate
the state of the PLL LOCK signal; a HIGH indicates a
locked condition. This discrete input can be used for other
purposes.
PLL_LOCKB: input from GP1010, indicates that a nega-
tive transition of the PLL LOCK signal (from locked to
unlocked state) has been detected and latched in the
GP1020. A HIGH indicates a negative transition. This bit
is cleared by the trailing edge of a read to BITE register
operation.
GLONASS BIT: TEST input from GLONASS front end. A
HIGH on this pin sets register bit HIGH. This discrete input
can also be used for other purposes.
SELF_TEST_EN: active HIGH. When inactive (LOW) the
self-test signal generator is disabled and TSIGN and
TMAG output pins are held LOW. When active the self-test
signal generator is enabled and TSIGN and TMAG output
pins are toggling. The injection back into the input of the
tracking channels is controlled by CHx_SIGNAL_SEL.
SELF_TEST_SOURCE: When LOW, the tracking chan-
nel 1 is used as a signal source for the self-test signal
generator. When HIGH, the tracking channel 2 is used as
a signal source for the self-test signal generator.
MEANDER: When HIGH, the self-test generator will
modulate the data bit stream with a meander. This is
required when GLONASS operation has to be tested.
CARR_MIX_ENB: When LOW, all carrier mixers operate
normally. When HIGH, all carrier mixers are disabled and
the incoming sign and magnitude data passes through
without being affected.
CHx_ACCUM_RESET Write Addresses 85, 89, 8D,
91, 95, 99_H and ALL_ACCUM_RESET Write Address
9D_H
These are write-only locations provided to allow resetting of
all the status bits associated with a given channel in
ACCUM_STATUS_A and ACCUM_STATUS_B.
ALL_ACCUM_RESET access will also clear the
NEW_STAT_DATA flag in ACCUM_STATUS_B register. When
these locations are written into, the data is don’t care. But if the
CNTTESTMODE bit (CHx_20MS_EPOCH register) is active,
G1 and G2 registers will be set at the 1023rd chip of the code
sequence. This operation accelerates the test process by gen-
erating accumulated data and status bits when the code steps to
the first chip and so generating a DUMP in the associated
channel.
CHx_CARR_CYCLE Read Addresses A3, A7, AB,
AF, B3, and B7_H
This register contains the 16 more significant bits of a variable
containing the number of CARRIER DCO cycles that occurred
during the last TIC period ending at a TIC. The value is sampled
and latched on the TIC. While reading measurement data
associated with a given channel, CHx_CARR_CYCLE must be
read last because the trailing edge of a read to this register will
release the overwrite protection mechanism of measurement
data for this channel.
CARR_CYCLE: PRINCIPLE OF OPERATION
In the CHx_CARR_CYCLE register and counter a TIC gen-
erates two consecutive actions:
1. It latches the 16 more significant bits of the cycle up counter
into CARR_CYCLE and the 2 less significant bits into
CARR_DCO_PHASE.
2. It resets the cycle up counter.
After each TIC, every time the carrier DCO accummulator
generates an OVERFLOW as a result of a carrier cycle being
completed, the cycle up counter counts up by one. The number
of bits needed for the counter was established as follows:
For GPS, the nominal CARRIER DCO frequency with no
Doppler and no oscillator drift compensation is 1·405396825
MHz, so in 100 ms, there will be about 140,540 cycles. For
GLONASS signals, the carrier DCO frequency wil vary depend-
ing on the particular satellite being tuned, between 1·429 - 0·6
MHz and 1·429 + 0·6 MHz, a maximum of 2·029 MHz, giving
202,900 cycles in 100 ms.
The maximum number of cycles, CARR_COUNT MAX, will
also depend on the maximum Doppler and oscillator drift com-
pensation to be allowed for, hence the counter must be able to
count to a number greater than 140,540 or 202,900.
The highest frequency required is then 2·029 MHz plus a few
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