GP1020 Datasheet, PDF (21/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

C/A CODE SELECTION
The CHx_CNTL register allows two different modes of pro-
gramming the CODE GENERATOR :
MODE 1: select the appropriate taps of G2 to generate
the GPS C/A code.
MODE 2: set the G2 register with the appropriate pat-
tern to generate the GPS or INMARSAT C/A
codes.
NOTE: When in MODE 2, the G2 register should be
loaded with a value representing its state at the
time of the second chip.
The difference between the two modes of programming the
C/A code is that MODE 2 allows the CODE GENERATOR to
synthesise the 8 INMARSAT C/A codes and MODE 1 does not,
but is more straightforward.
The following table gives the pattern of bits 3 to 0 or 7 to 4
to select a particular tap (used in MODE 1 of the CHx_CNTL
register) :
Bit
Pattern
Tap
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1xx0
9
1xx1
10
The table below shows the bit setting required to select the
appropriate taps which will decode the 37 possible GPS PRN
signal numbers when in MODE 1 and the bit setting required to
set the G2 register in the second chip state for all GPS and
INMARSAT C/A codes when in MODE 2.
Note that the list does not show all the possible tap and
bit setting combinations. Tap combinations which are not listed
can also be used if required.
GPS PRN
signal no.
MODE 1
bit setting
7 to 0
Selected
taps
MODE 2
bit setting
9 to 0
1
0001 0101
2 EXOR 6
3F6_H
2
0010 0110
3 EXOR 7
3EC_H
3
0011 0111
4 EXOR 8
3D8_H
4
0100 1xx0
5 EXOR 9
3B0_H
5
0000 1xx0
1 EXOR 9
04B_H
6
0001 1xx1
2 EXOR 10 096_H
7
0000 0111
1 EXOR 8
2CB_H
8
0001 1xx0
2 EXOR 9
196_H
9
0010 1xx1
3 EXOR 10 32C_H
10
0001 0010
2 EXOR 3
3BA_H
11
0010 0011
3 EXOR 4
374_H
12
0100 0101
5 EXOR 6
1D0_H
13
0101 0110
6 EXOR 7
3A0_H
14
0110 0111
7 EXOR 8
340_H
15
0111 1xx0
8 EXOR 9
280_H
16
1xx0 1xx1
9 EXOR 10 100_H
17
0000 0011
1 EXOR 4
113_H
18
0001 0100
2 EXOR 5
226_H
19
0010 0101
3 EXOR 6
04C_H
20
0011 0110
4 EXOR 7
098_H
21
0100 0111
5 EXOR 8
130_H
22
0101 1xx0
6 EXOR 9
260_H
GP1020
GPS PRN
signal no.
MODE 1
bit setting
7 to 0
Selected
taps
MODE 2
bit setting
9 to 0
23
0000 0010
24
0011 0101
25
0100 0110
26
0101 0111
27
0110 1xx0
28
0111 1xx1
29
0000 0101
30
0001 0110
31
0010 0111
32
0011 1xx0
33
0100 1xx1
34 *
0011 1xx1
35
0000 0110
36
0001 0111
37 *
0011 1xx1
201
n/a n/a
202
n/a n/a
205
n/a n/a
206
n/a n/a
207
n/a n/a
208
n/a n/a
209
n/a n/a
211
n/a n/a
1 EXOR 3
4 EXOR 6
5 EXOR 7
6 EXOR 8
7 EXOR 9
8 EXOR 10
1 EXOR 6
2 EXOR 7
3 EXOR 8
4 EXOR 9
5 EXOR 10
4 EXOR 10
1 EXOR 7
2 EXOR 8
4 EXOR 10
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
267_H
120_H
270_H
0E0_H
1C0_H
380_H
22B_H
056_H
0AC_H
158_H
2B0_H
058_H
18B_H
316_H
058_H
2C4_H
10A_H
3E3_H
0F8_H
25F_H
1E7_H
2B5_H
10E_H
*C/A Codes 34 and 37 are common
NOTE: PRN sequences 33 to 37 are reserved for other uses (e.g.
ground transmitters).
The table below lists the required setting of the register bit 0
to generate the GLONASS C/A code or the GLONASS-like test
C/A code. Note that bit 10 must be HIGH to select GLONASS
rather than GPS codes.
Bit 0 setting
MODE 1 & 2
Code type
Selected G1 taps
0
GLONASS
5 EXOR 9
1
GLONASS TEST 3 EXOR 5 EXOR 6 EXOR 9
In update mode, the C/A code generated by the CODE
GENERATOR can be changed at any time but the next accumu-
lated data following the command will not be valid. The MODE
bit cannot be modified without disabling the clock phases when
in UPDATE mode otherwise the C/A code generated will not be
valid. This is not the case when starting a PRESET sequence.
To provide a clean switch between GLONASS and GPS
modes of operation for a specific channel, it is necessary to
proceed as follows: Disable propagation of the clock phases to
this tracking channel by selecting the appropriate bit in the
RESET_CNTL register, then select the desired mode of opera-
tion GLONASS or GPS and re-enable the propagation of the
clock phases. If the clock phases propagation are not disabled,
the next accumulated data will not be valid.
When the dithering code has been selected, the dithering arm
will use the EARLY code for a period of 20 C/A codes, the LATE
code for the next 20 C/A codes and this process of dithering
between EARLY and LATE code will be repeated indefinitely.
The dithering arm will use the EARLY code for the first 20 ms
EPOCH following a SLEW or a PRESET operation.
Upon MASTERRESET, CHx_CNTL bits are set to the
states given in the following Table.
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