GP1020 Datasheet, PDF (29/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

function will never be selected. For standard operation a single
0 is required and all the other bits must be at 1. The position of
the 0 in the register allows the duty cycle of the data inversion
function to be set as shown below:
Bits 10 9 8 7 6 5 4 3 2 1 0
Description
0 0 0 0 0 0 0 0 0 0 0 Power up condition, the
data inversion function
is always selected.
1 1 1 1 1 1 1 1 1 1 0 The data inversion
function is always
selected.
1 1 1 1 1 1 1 1 1 0 1 The data inversion
function is selected 10
times in 11.
1 1 1 1 1 1 1 1 0 1 1 The data inversion
function is selected 9
times in 11.
0 1 1 1 1 1 1 1 1 1 1 The data inversion
function is selected 1
time in 11.
1 1 1 1 1 1 1 1 1 1 1 The data inversion
function is never
selected.
TIMER_CNTL Write Address C2_H
Register bit mapping
Bit
Name
Description
0 TIC_PERIOD
When LOW, the TIC period is
175 ns3571,428 = 99·9999ms.
When HIGH, the TIC period is
175 ns 3 51,948 = 9·0909ms.
TIC_PERIOD is set LOW by
reset.
1 INT_MASKB
When LOW, the interrupt output
signal is disabled, the INT OUT
pin is held LOW and the status
bits are not sampled by an on-
chip or an externally generated
interrupt. When HIGH, the int-
errupt output signal is enabled
and the status bits will be
sampled by an interrupt.
INT_MASK is set LOW by
reset.
2 TIC_SOURCE
When LOW, TIC source is
internal, when HIGH, TIC
source is external (provided by
a companion GP1020 through
TICIN pin). TIC_SOURCE is
set LOW by reset.
GP1020
Register bit mapping
Bit
Name
Description
3 INT_SOURCE
When LOW, the signal used to
latch the state of status bits and
the results of the STAT_CHECK
block is the positive edge in Intel
mode or the negative edge
in Motorola mode of the
INT signal generated on-chip.
When HIGH, the edge
of the INT signal provided on
INTIN pin of the device by a
companion GP1020 is used
instead. INT_SOURCE is set
LOW by reset.
4 TEST_OP/MARKB When LOW, the GP1020
MARK output pin will output
the time MARK output. When
HIGH, the output will be driven
by a signal selected by the
CH1_DUMP/OSC_CHECK
bit (bit 8) of this
TIMER_CNTL register.
TEST_OP/MARKB is set
LOW by reset.
7 to 5
Mark Feedback active edge
selection, with the following
encoding:
Bit
765
Selected
function
000
001
010
011
100
101
110
111
FB1↑
FB1↓
FB2↑
FB2↓
FB3↑
FB3↓
TICOUT↑
TICOUT↓
The FBx↑ (rising edge) and
FBx ↓ (falling edge) signal edges
are used to calculate the
pulse width of the Mark
Feedback signal. This calcula-
tion allows monitoring of the
pulse width and verification
that the result is in accordance
with the 1 ms ± 0.01 ms
specification. The TIC OUT
signal is also available as
feedback for test purposes.
Bits 7 to 5 are set LOW
by reset.
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