GP1020 Datasheet, PDF (17/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

DETAILED DESCRIPTION OF REGISTERS
The registers are listed in alphabetical order and not in
address order to allow easy reference to each section.
ACCUM_STATUS_A Read Address 82_H
Register bit mapping
Bit
Bit name
LSB 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB 15
CH1_NEW_ACCUM_DATA
CH2_NEW_ACCUM_DATA
CH3_NEW_ACCUM_DATA
CH4_NEW_ACCUM_DATA
CH5_NEW_ACCUM_DATA
CH6_NEW_ACCUM_DATA
not used
not used
CH1_EARLY_LATEB
CH2_EARLY_LATEB
CH3_EARLY_LATEB
CH4_EARLY_LATEB
CH5_EARLY_LATEB
CH6_EARLY_LATEB
not used
NEW STAT_DATA
REGISTER OPERATION
ACCUM_STATUS_A is a latch register containing the state
of status bits prevailing at time of sampling. The status bits are
sampled and latched on the positive edge of every INT OUT or
INT IN signal. They can also be sampled and latched on request
by performing a write operation to STATUS_LATCH (location
80_H). Latching the status bits ensures glitch-free reading of
ACCUM_STATUS_A.
BIT DESCRIPTION
The following bits are all active HIGH:
CHx_NEW_ACCUM_DATA status bit indicates if there is
new accumulated data available to be read. Each indi-
vidual bit can be cleared with a write operation at
CHx_ACCUM_RESET location or by disabling the propa-
gation of clocks (CHx_RSTB bits of RESET_CNTL). This
also releases the overwrite protection.
Each bit is also cleared on the trailing edge of a read of
the associated Q_PROMPT register. If new accumulated
data becomes available after ACCUM_STATUS_A bits
have been latched, the overwrite protection is not cleared
while reading the Q_PROMPT register and the
CHx_NEW_ACCUM_DATA bit will be set at the next
latching of ACCUM_STATUS_A.
CHx_EARLY_LATEB status bit indicates whether the
accumulated data on the dithering arm of the tracking
channel results from correlation with early or late code. A
HIGH indicates an EARLY code and a LOW indicates a
LATE code. Each individual bit is updated at each DUMP
when the overwrite protection is not active. When the
Early-Minus-Late code is selected for a particular channel,
this status bit has no meaning.
NEW_STAT_DATA status bit when HIGH indicates that
new statistical data is available in the STAT_CHK_SIGN
and STAT_CHK_MAG registers. It is cleared when a
STAT_CHK_MAG read operation is performed if a valid
state had been latched previously or by a write operation
at ALL_ACCUM_RESET location. The first statistical
data after a power up is not representative and should be
cleared. All status bits are reset by a hardware or software
master reset.
ACCUM_STATUS_B Read Address 83_H
Register bit mapping
Bit
Bit name
LSB 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MSB 15
CH1_MISSED_ACCUM
CH2_MISSED_ACCUM
CH3_MISSED_ACCUM
CH4_MISSED_ACCUM
CH5_MISSED_ACCUM
CH6_MISSED_ACCUM
not used
not used
CH1_OVFL_ACCUM
CH2_OVFL_ACCUM
CH3_OVFL_ACCUM
CH4_OVFL_ACCUM
CH5_OVFL_ACCUM
CH6_OVFL_ACCUM
not used
not used
GP1020
REGISTER OPERATION
ACCUM_STATUS_B bits are sampled and latched on the
positive edge of every INT OUT or INT IN signal. They can also
be sampled and latched on request by performing a write
operation to STATUS_LATCH (location 80_H).
BIT DESCRIPTION
CHx MISSED_ACCUM status bit indicates if there has
been missed accumulated data. When active HIGH, this
status bit is latched until (i) a master reset (hardware or
software) or (ii) a write operation to CHx_ACCUM_RESET
with don’t care data or (iii) the propagation of clocks is
disabled (CHx_RSTB bits of RESET_CNTL).
CHx_OVFL_ACCUM status bit indicates if there has
been an overflow in any of the channel accumulated data
registers. This bit is active HIGH and is updated at each
DUMP when the overwrite protection is not active. It gets
reset whenever the associated CHx_ACCUM_RESET is
written into with don’t care data or upon a master reset
(hardware or software) or by disabling the propagation of
clocks (CHx_RSTB bits of RESET_CNTL).
ADD_DAT_TST Read/Write Address C7_H
This register is used to test the address bus and data bus
hardware connections to the inputs of the chip. It allows the
system to verify that there is no short between pins or input lines
in the chip or on the board.
Register bit mapping
Bit
Description
15 to 8
7 to 0
Contents of address bus or most
significant bits of data bus.
Contents of least significant bits of
data bus.
REGISTER OPERATION
This register is a read/write register. Upon a master reset
(software or hardware) the register is cleared. When a write is
performed at address AA_H or 55_H the most significant bits of the
register will be loaded with the address bus value present on the
bus, AA_H or 55_H if the address bus is working properly and the
least significant bits of the register will keep their previous value.
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