GP1020 Datasheet, PDF (4/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions (unless otherwise stated):
Supply voltage, V_DD = 5V ±10%; Ambient Temperature, T_AMB = 0°C to 170°C (CG grade),240°C to 185°C (IG grade).
DC CHARACTERISTICS
Characteristic
Min.
Value
Typ.
Units
Max.
Conditions
Supply current, I_DD, chip fully active
100
mA
CMOS inputs with pullup resistors to V_DD : RTCINT,
MASTER/SLAVE, MARKFB (3:1), NANDA, NANDB,
WPROG, ALE
Input voltage high
Input voltage low
Pullup resistor
0·8V_DD
V
0·2V_DD
V
20
75
250
kΩ
CMOS inputs with pulldown resistors to V_SS : MOT/INTEL,
CLKSEL, INT IN, TIC IN
Input voltage high
Input voltage low
Pulldown resistor
0·8V_DD
V
0·2V_DD
V
20
75
250
kΩ
CMOS inputs without either pullup or pulldown resistors:
MASTERRESET, CS, WEN, RW, MASTERCLK (note 1),
SLAVECLK, A (8:1), D (15:0), TCK, TDI, TMS, TRST
Input voltage high
Input voltage low
Input leakage current
0·8V_DD
V
0·2V_DD
V
1
10
µA
V_SS<V_PIN<V_DD
TTL inputs with pullup resistors to V_DD : SIGN (9:0),
MAG (9:0), PLLLOCKIN, GLONASSBIT
Input voltage high
2·0
V
Input voltage low
0·8
V
Pullup resistor
20
75
250
kΩ
TTL inputs with pulldown resistors to V_SS : TSCAN, TCKS,
TDI1, TMS1, TMS2
Input voltage high
2·0
V
Input voltage low
0·8
V
Pulldown resistor
20
75
250
kΩ
Input for low level clocks: MASTERCLK (note 1)
Peak to peak sinewave
Power level 1 outputs: TMAG, TSIGN, TDO, TDO (7:1),
NANDOP
Output voltage high
Output voltage low
600
V_DD21 V_DD20·5
0·2
0·4
Power level 3 outputs: 100/219kHz, INT OUT, SAMPCLK,
TIC OUT, BITE CNTL, DISCOP, TIMEMARK
Output voltage high
Output voltage low
V_DD21 V_DD20·5
0·2
0·4
mV AC coupled
V
I_OH = 21·5mA
V
I_OL = 1·5mA
V
I_OH = 24·5mA
V
I_OL = 4·5mA
Power level 1 outputs with tri-state: MAG (9:2), SIGN (8:2),
TCK (7:1)
Output voltage high
Output voltage low
V_DD21 V_DD20·5
0·2
0·4
Output leakage current
10
Power level 3 output with tri-state: SLAVECLK
Output voltage high
Output voltage low
Output leakage current
V_DD21 ^VDD^20·5
0·2
0·4
10
V
I_OH = 21·5mA
V
I_OL = 1·5mA
µA
V_SS<V_PIN<V_DD
V
I_OH = 24·5mA
V
I_OL = 4·5mA
µA
V_SS<V_PIN<V_DD
Power level 6 output with tri-state: D (15:0)
Output voltage high
Output voltage low
Output leakage current
V_DD21
V_DD20·5
0·2
0·4
10
V
I_OH = 29·0mA
V
I_OL = 9·0mA
µA
V_SS<V_PIN<V_DD
Bias output: BIAS
Special output to be used only as shown in Fig. 12 (page 8)
NOTE 1. The input MASTERCLK may be driven by either CMOS logic levels or by a low amplitude sinewave if the BIAS pin is connected as shown
in Fig. 12.
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