GP1020 Datasheet, PDF (33/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

10. Short Glitch Recovery
Refer to the block diagram shown in Fig. 17 for the following
discussion.
It is assumed that the RTC selected provides an interrupt
output signal which occurs periodically, every 100ms or every
second. The interrupt is sent to both the GP1020 and the
processor system. Within the GP1020, the interrupt is connected
to the RTC_INT input pin of the GP1020. Its edge enables the
RTC_DELAY counter. This counter is clocked by a signal with a
period of 2.275µs and increments until the next TIC. The TIC
causes the value of RTC_DELAY to be latched in order to be
read with the measurement data.
GP1020
If data bit synchronisation cannot be achieved on a given channel,
but proper code and carrier lock are obtained, the software should
jump to the data bit synchronisation algorithm. If lock is not obtained,
then the software should jump to the search algorithm. Given the
magnitude of error terms (summed) and the worst case error allowed
in order to keep data bit synchronisation, it is possible to calculate the
length of the longest permitted power glitch. See Fig. 20.
11. TIME MARK Generator
The Time Mark generator is designed to provide a one second
Time Mark output signal which can be synchronised with a given time
REAL TIME ^{RTC_INT AT 1 SEC RATE}
CLOCK
MICROPROCESSOR
SYSTEM
CLOCK (439·56kHz)
COUNTER
ENABLE
100ms TIC
RESET
RTC_DELAY
GP1020
NOTES
1. Latch counter value
saved on TIC.
2. Register read with
measurement data.
Fig. 17 RTC block diagram
When the processor receives the RTC interrupt, it reads the RTC
time. Alternatively, RTC_TIC may not be routed to the processor, but
instead, every time the RTC_TIC_ACK status bit of
MEAS_STATUS_B is set in the GP1020, the software reads the
RTC time. With this information, together with the contents of
RTC_DELAY, the software is able to determine first the delay
between the RTC and the system clock and secondly, with consecu-
tive readings, the RTC drift can be evaluated. These two pieces of
base, such as the receiver time base, the GPS time or UTC. The
Time Mark is generated after a certain programmable delay relative
to the TIC.
The architecture chosen (see Fig. 19) involves minimal
hardware being clocked at a high rate and so gives low power
consumption.
As an example, to synchronise TIME MARK to UTC, the software
could have the following sequence of operations (see Fig. 21):
RTC TIME READ HERE
BY PROCESSOR
100ms TIC
POSITION FIX COMPUTED ON THIS TIC.
TIC IS GPS TIME TAGGED.
t_s
RTC_INT
RTC_DELAY
D
NOTES
1. D = delay between RTC timebase and system time t_s.
2. Consecutive measurements of D give an indication of RTC drift.
3. Resolution of D is a function of input clock to RTC_DELAY counter.
Fig. 18 RTC timing diagram
information are stored in non-volatile RAM every time they are
calculated. After occurrence of a power glitch, the 100ms_TIC
timebase restarts free running but with an arbitrary phase relation-
ship with respect to the TICs before the power glitch. The RTC
interrupt process occurs again as described above and it is possible
to relate the new system TIC time relative to the previous. Ideally, this
process is precise enough such that the data bit sync is not lost and
all the channel control registers can be reprogrammed with proper
values. Once the timing relationship is known, the PRESET mode
can be used to resume tracking of the signals.
1. Acquire measurement data at time to (on an arbitrary TIC)
2. Solve for UTC at measurement instant UTC (t₀). Note that the
solution can only be accurate to within the hardware propa-
gation delays in the receiver, typically a few microseconds,
unless these delays are calibrated and UTC solution is
corrected accordingly.
3. Compute on which 100ms TIC, t_m, to take the next sample of
measurement data such that:
UTC TIME MARK 2 t_m = d₁1d₂
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