GP1020 Datasheet, PDF (32/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
of half code chips). The slew will be effective on the next dump.
Thus this dump will generate don’t care accumulated data and
as a minimum, the Q_PROMPT register will have to be read to
release the overwrite protection mechanism.
Note that it is only possible to delay the phase of the code. It
cannot be advanced.
5. DATA BIT SYNCHRONISATION Related
Operations
When the right code phase is found, the carrier loop is closed.
The CARR_INCR_HI and CARR_INCR_LO registers can be
reprogrammed at any time to close the feedback loop and
resume code tracking.
The Data Bit Sync algorithm should find the data bit transition
instant. The processor calculates the present one millisecond
epoch and programs this value into the 1MS_EPOCH register.
The effect is immediate.
After each DUMP, the epoch counter value can be read within
1ms and preferably at the same time as the integrate and dump
registers. This provides a means of verifying that the epoch
counters are indeed properly programmed. Programming the
epoch counter in the 500µs period following a valid
CHx_NEW_ACCUM_DATA should ensure that the program-
ming becomes effective before the next DUMP.
Alternatively, the EPOCH registers can be left free-running
and the delta-epoch can be added by the software each time it
reads the EPOCH registers. However, the dithering between
early and late code will be controlled by the actual contents of the
EPOCH registers, which will not necessarily be in phase with
data bit boundaries.
6. READING the MEASUREMENT Data
At every occurrence of a TIC, the measurement data is
latched in measurement data registers. The TIC does not
generate any interrupt signal, however, it does set the
CHx_NEW_MEAS_DATA status bits of the MEAS_STATUS_A
register. This register is normally always read while collecting
accumulated data once every 505.05 microseconds (The INT
OUT signal rate). The software tests the
CHx_NEW_MEAS_DATA status bits to determine if new meas-
urement data is available to be read. For each channel, the last
measurement data register to be read must be
CHx_CARR_CYCLE because the trailing edge of this read
releases the overwrite protection mechanism and clears the
corresponding CHx_NEW_MEAS_DATA bit. The software
must also read the MEAS_STATUS_B register to determine if
there was any missed measurement data or if phase and epoch
counters were being slewed during the last TIC period, indicating
invalid measurement data for the affected channel.
7. The PRESET Mode
Each tracking channel can be individually programmed to
operate either in UPDATE or PRESET mode. A given channel
is programmed in PRESET mode by writing a HIGH into the
PRESET/UPDB bit of the CHx_CNTL register.
The sequence of operations is as follows:
1. Write into CHx_CNTL to select the PRESET mode together
with the appropriate code, code format on the dithering arm, etc.
Since the PRESET mode is selected, the new selected code and
code format will be effective on the next TIC.
2. Between the instant at which the PRESET mode is selected
and the next TIC, the tracking channel will continue to operate
normally, that is, it will provide accumulated data for the signal
being tracked.
3. The INCRement registers of the CODE and CARRIER DCO’S
have to be loaded with the appropriate frequencies for the new
signal to be tracked either immediately or only after the TIC has
occured if it is desired not to disturb the tracking in effect.
4. Load the following PRESET registers:
PRESET_PHASE: Will set the code DCO phase.
CODE_SLEW: Will set the code phase.
1MS_EPOCH: Will set the 1 ms epoch.
20MS_EPOCH:Will set the 20 ms epoch.
It is important to have the PRESET mode selected prior to
programming the CODE_SLEW and the EPOCH registers in
order to have these new values effective on the next TIC as
opposed to immediately if they were programmed under UP-
DATE mode.The PRESET_PHASE register can be programmed
either before or after selecting the UPDATE mode. In PRESET
mode the value to program in the CODE_SLEW register repre-
sents the delay between the TIC and the first code chip.
To ensure correct PRESET of EPOCH counters, the loading
of PRESET registers has to be completed prior to the TIC relative
to which the PRESET values are computed. Thus the operation
has to take place within a TIC window.
It is important to load the 20MS_EPOCH register last in the
loading sequence. The trailing edge of a write to this register
enables the PRESET operation on the next TIC.
5. After the PRESET operation has taken place on a TIC, the
PRESET/UPDB bit of the CNTL register is reset and the channel
goes back to UPDATE mode. It is possible that the code phase
has to be slewed so the CODE_SLEW register when loaded will
then cause a slew to start on the next DUMP.
On the TIC, the measurement data saved for the signal being
tracked so far will be valid. The measurement data registers (or
at least CHx_CARRIER_CYCLE register) must either be read or
a write operation to CHx_MEAS_RESET must be made in order
to clear the measurement status bits and allow measurement
data acquisition on the next TIC for the new signal to be tracked
under PRESET mode.
8. The TIC GENERATOR and the Interrupt Time
Base
The interrupt time base consists of a free-running counter
providing a pulse of constant period on a GP1020 output pin. The
frequency uncertainty on this time base will be identical to the
system oscillator drift. The interrupt time base shares some
dividers with the TIC generator. The period of this time base is
175ns 3 2886 = 505.05µs at power up, but may be changed by
programming TIMER_CNTL register, and is always an exact
sub-multiple of the TIC time base. Every 198th (or 18th) interrupt
pulse at default rate will occur at the same time as a 100ms (or
9.0909ms) TIC, not taking into account propagation delays.
Either INT IN or INT OUT (as controlled by the INT_SOURCE bit
of the TIMER_CNTL register) is used to sample and latch the
status bits and statistics on incoming sign and magnitude bits.
The interrupt is maskable. The INT_MASKB bit of the
TIMER_CNTL register when set LOW forces the logic level on
the output pin to LOW. A master reset will set this bit LOW.
9. SIGNAL PATH DELAY Introduced by Hardware
Signal Processing
The signal path delay has two components as follows:
D_t = Total path delay = D_a + D_d
D_a = Analogue path delay; varies with temperature and
component tolerances.
D_d = Digital path delay; constant if oscillator drift
variations are neglected.
For GPS signals, D_d = 125ns. This delay is the time from the
sampling edge of the SIGN and MAG bits in the GP1010 (SAMP
CLK) to the performance of the correlation in the GP1020 on these
same SIGN and MAG bits (100ns) plus the delay between the
correlation and the TIC clock phases in the master GP1020 (25ns).
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