GP1020 Datasheet, PDF (34/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
Where UTCTIME MARK = Desired time mark synchronised to
a UTC second.
d₁ = k 3 (time between TICS),
where k=INTEGER and d₁>Nav solution computation
delay.
d₂ = time offset (with 50 ns resolution) between time
mark and 100ms_TIC labelled t_r
d₂ < (time between TICS)
• ^{4. Acquire measurement data at t}m
• ^{Compute Nav solution at t}m
Propagate Nav solution at UTC
•• Given the oscillator drift, the delay of 25 ns added by
TIME_MARK_GEN block and the calibrated propagation
delay, compute DOWN_COUNT, the value to program into
the programmable down counter to delay the time mark by d₂.
5. Program down counter with DOWN_COUNT before the
occurrence of t_r.
6. Output ARINC Data within 200ms after t_r (following ARINC
743)
7. Locate t_m11 and go back to step 4.
40MHz MASTERCLOCK
47
CLOCK
GENERATOR
4571, 428
20-BIT
COUNTER
CLK
CONTROL
LOGIC
CNTL
100ms TIC
20-BIT
PROGRAMMABLE
DOWN COUNTER
MARKFBx
EXTERNAL
LINE
DRIVERS
GP1020
1 SEC. TIME MARK
t_s1
100ms TIC
Fig. 19 Block diagram of TIME MARK generator
t_s2 t_s3
RTC TIC
D₁
D2
DRTC = (RTC22RTC12RTCDRIFT)
RTC1
RTC2
NOTES
1. t_s2 = t_s12D₁1DRTC1D₂ (± error terms)
2. ERROR TERMS: in ts₁ : Equal to error terms of GPS time computation
while getting the NAV solution
in D₁ : Can be too long or too short by r,
where r = RTC_DELAY counter clock period
in D₂ : Same as D₁
in DRTC : Residual error in RTC drift estimate,
= (effective RTC_DRIFT)2(estimated RTC_DRIFT)
Fig. 20 Timing diagram of a short glitch
NAV SOLUTION
COMPUTATION
DELAY
100ms TIC
t₀
COMPUTE t_m
d1
t_m
t_r
TIME BETWEEN TICs
IS CONSTANT
d2
TIME
OUTPUT
UTC TIME MARK
Fig. 21 TIME MARK timing diagram
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