GP1020 Datasheet, PDF (42/44 Pages) Zarlink Semiconductor Inc – SIX-CHANNEL PARALLEL CORRELATOR CIRCUIT FOR GPS OR GLONASS RECEIVERS

GP1020
PIN CONNECTIONS FOR A SIMPLIFIED SYSTEM (continued)
Pin No.
81
82 and 83
84
85 and 86
87
88 and 89
90
91 and 92
93
94
95
96 and 97
98 and 99
100
101
102 and 103
104 to 107
108 and 109
110
111
112 and 113
114
115 to 120
Signal name
V_SS
D6 and D7
WPROG
NANDA and B
TDO
TCK and TRST
NANDOP
TMS and TDI
MARKFB3
TDO7
DISCOP
TDO6 and TDO5
D8 and D9
V_SS
V_DD
D10 and D11
TDO4 to TDO1
D12 and D13
V_DD
V_SS
D14 and D15
ALE
A1 to A6
Description
Ground
Data bus
Bus timing mode select
Test/spare gate inputs
Boundary Scan output
Boundary Scan clock and Reset
Test/spare gate output
Boundary Scan select and input
Time Mark driver feedback
Test Data Output 7
General purpose output pin
Test Data Outputs 6 and 5
Data bus
Ground
Positive supply
Data bus
Test Data Outputs 4 to 1
Data bus
Positive supply
Ground
Data bus
Address Latch Enable
Address bus
Connection
0V
To microprocessor
Low (see note 5)
Low
Leave open
Both low
Leave open
Both low
Low
Leave open
Leave open
Leave open
To microprocessor
0V
15V
To microprocessor
Leave open
To microprocessor
15V
0V
To microprocessor
To microprocessor
To microprocessor
Notes
1. The action of WEN and RW is given in the table at the foot
of page 3.
2. In the above list, it is assumed that only one Front-end is
being used and that it is connected to SIGN0 and MAG0.
Any other SIGN and MAG pair may be chosen if desired.
3. Unused inputs are listed in the above table as tied low (to
ground) so that they are not left floating.
4. Connections listed ‘To microprocessor’ may, in some
systems, be made via glue logic such as address latches.
5. WPROG is used to modify the Write timing. For most
applications, WPROG should be tied low. For use with an
Intel 486, it may be better to tie WPROG high to delay the
start of the Write operation until after the address decode
in the GP1020 has settled.
6. ALE is listed as ‘To microprocessor’ but it is possible in
systems with WPROG tied low to have ALE tied high to
make the latches in the GP1020 transparent if the address
bus is externally latched for the write or read operation.
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